Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-07-21
2004-04-06
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S003000, C714S011000
Reexamination Certificate
active
06718483
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fault tolerant circuit and an autonomous recovering method.
2. Description of the Related Art
A conventional circuit system having a fault tolerance is known. In the conventional circuit system, when any failure has occurred in a part of a plurality of logic gates, a fault circuit block including the failed logic gate is not used or cut down from the circuit system. Thus, the function stop of the whole circuit system is prevented in the conventional circuit system.
Another conventional circuit system having a fault tolerance system is known. Such a conventional circuit system includes a plurality of circuit blocks and redundant circuit blocks. The redundant circuit blocks have the same circuit structures as the circuit blocks. When any failure has occurred in a part of the logic gates, the redundant circuit block corresponding to the failure circuit block including the failed logic gate is used in place of the failed circuit block.
In conjunction with the above description, a microprocessor with an autonomous recovering function is described in Japanese Laid Open patent application (JP-A-Heisei, 2-171837). In this reference, the microprocessor does not have a function-changeable circuit block. This conventional microprocessor does not reproduce a function of troubled circuit blocks. This conventional microprocessor does not have data for reproducing a replica of the troubled circuit blocks. Even if the trouble is induced in this conventional microprocessor, this conventional microprocessor does not reproduce the operation of the troubled circuit blocks.
Japanese Laid Open patent application (J-PA-Heisei, 8-255500) discloses an apparatus and method for recovering an ASIC memory based on the result of testing the ASIC memory. This conventional example includes a test circuit, an autonomous recovery circuit, a memory array and a plurality of redundant lines in the memory array. In the conventional example, the ASIC memory is tested on a chip and recovered based on the rest result. In the recovering step, a method is contained for testing and autonomously recovering the ASIC memory on a chip. An original address position -related to any trouble Is redirected to an address at-least one redundant line is mapped, by using a recovery circuit.
Japanese Laid Open Patent Application (JP-A-Heisei, 9-311824) discloses a built-in autonomous recovery system for an assembly type memory. This conventional example is constituted of a system for attaining an on-chip recovery function using a redundancy circuit in a memory array The conventional autonomous recovery system has a memory array, a recovery circuit, and an on-chip clock generator. The recovery circuit is connected to the memory array. The on-chip clock generator is connected to the recovery circuit. The memory array includes a plurality of I/O memory blocks, a plurality of redundant I/O memory blocks, a plurality of row lines, and a plurality of redundant memory lines. The plurality of row lines intersect the plurality of I/O memory blocks. The plurality of row lines are connected to a plurality of redundant row memory lines. The plurality of I/O memory blocks are connected to a plurality of redundant I/O memory blocks. Also, this recovery circuit recovers a failed row line by use of the redundant row line. Moreover, the recovery circuit recovers a failed I/O memory block by use of the redundant I/O memory block. Also, the on-chip clock generator generates and outputs a trigger signal to the recovery circuit for actuating this recovery circuit.
Japanese Laid Open patent application (JP-A-Heisei, 10-84275) discloses a logic circuit. This conventional logic circuit can attain a fault tolerant property. This conventional logic circuit is provided with a control circuit and a programmable logic cell array. The programmable logic cell array is composed of a plurality of programmable logic cells, which are connected to each other. Each of the plurality of programmable logic cells has an autonomous checking function. When any trouble has occurred in one logic cell, the logic cell transmits a fault occurring signal to the control circuit to indicate that the trouble has occurred in the logic cell itself, independent from another circuit. When the control circuit is received the fault occurring signal, the control circuit stops the sending of a clock signal to the logic cell array, and carries out a reprogramming process of the logic cell array.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a fault tolerant circuit and an autonomous recover method, for detecting a fault.
Another object of the present invention Is to provide a fault tolerant circuit and fault tolerant method for detecting a failed portion including the fault tolerant circuit Still another object of the present invention is to provide a fault tolerant circuit and an autonomous recover method, for detecting a failed portion including the fault tolerant circuit and for controlling a remaining portion other than the failed portion to execute a part of functions executed by the fault tolerant circuits.
Still another object of the present invention to to provide a fault tolerant circuit and an autonomous recovery method, for detecting a failed portion including the fault tolerant circuit and for controlling a remaining portion other than the failed portion to execute a part of functions selected based on predetermined priorities.
In order to achieve an aspect of the present invention a fault tolerant circuit including: a circuit section having a plurality of circuit sections provided to execute a plurality of functions, in which each of the plurality of functions has a pre-determined priority level: a detecting circuit detecting whether or not a part of the plurality of circuit sections is failed: and a reconstructing circuit reconstructing a remaining part of the circuit section other than the failed part of the plurality of circuit sections to execute a part of the plurality of functions which is selected based on the pre-determined priority levels when the detecting circuit detects that the part of the plurality of circuit sections is failed.
In the fault tolerant circuits the plurality of circuit sections are electrically connected, and the reconstructing circuit changes the electrical connections between the remaining part of the circuit section other than the failed part of the plurality of circuit sections to execute the part of the plurality of functions selected based on the pre-determined priority levels when the detecting circuit detects that the part of the plurality of circuit sections is failed.
The fault tolerant circuit may further includes a memory storing a plurality of function data and a plurality of segment data, in which each of the plurality of function data corresponds to one of the plurality of functions and each of the plurality of segment data indicates a part of the plurality of circuit sections which are needed for executing the corresponding function, and the reconstructing circuit refers to the memory to retrieve the plurality of function data and the plurality of segment data, when the detecting circuit detects that the part of the plurality of circuit sections is failed, and reconstructs the remaining part of the circuit section other than the failed part of the plurality of circuit sections based on the plurality of retrieved function data and the plurality of retrieved segment data, to execute the part of the plurality of functions which is selected based on the pre-determined priority levels.
In the fault tolerant circuit, each of plurality of circuit sections includes a switching portion for controlling the corresponding circuit section to supply voltage, and the detecting circuit controls the switching portions of the failed part of the plurality of circuit sections to stop supplying the voltage.
In the fault tolerant circuit, each of plurality of circuit sections includes a switching portion for controlling the corresp
Iqbal Nadeem
NEC Corporation
LandOfFree
Fault tolerant circuit and autonomous recovering method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fault tolerant circuit and autonomous recovering method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fault tolerant circuit and autonomous recovering method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3240217