Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2005-06-21
2005-06-21
Rinehart, Mark H. (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C326S030000
Reexamination Certificate
active
06910089
ABSTRACT:
A backplane apparatus for an electronic device enclosure includes a common bus comprising a plurality of signal lines, each signal line having a current limiting element, RA. Isolation circuitry is provided for electrically coupling each of the plurality of signal lines of the common bus to a corresponding plurality of signal lines of the electronic device to enable signal communication between the common bus and the electronic device through the isolation circuitry. In one embodiment, the backplane apparatus further comprises connectors to enable removably attaching the electronic devices such as disk drives. In one embodiment, the isolation circuitry coupling each signal line of the common bus to the connector comprises an inline resistor, RD. The isolation circuitry associated with some of the signal lines may include pull up resistors. The values of RA and RD are selected to ensure that the common bus meets pre-determined current and voltage requirements so that the common bus can change states even if one or more of the devices fail by shorting to ground.
REFERENCES:
patent: 4445048 (1984-04-01), Graham
patent: 5019728 (1991-05-01), Sanwo et al.
patent: 5046072 (1991-09-01), Shimizu et al.
patent: 5224021 (1993-06-01), Takada et al.
patent: 5382841 (1995-01-01), Feldbaumer
patent: 5564024 (1996-10-01), Pemberton
patent: 5568060 (1996-10-01), Bartholomay et al.
patent: 5568063 (1996-10-01), Takekuma et al.
patent: 5572685 (1996-11-01), Fisher et al.
patent: 5612634 (1997-03-01), MacKenna
patent: 5620331 (1997-04-01), Los et al.
patent: 5663661 (1997-09-01), Dillon et al.
patent: 5721497 (1998-02-01), Novak
patent: 5767695 (1998-06-01), Takekuma et al.
patent: 5945886 (1999-08-01), Millar
patent: 5955703 (1999-09-01), Daly et al.
patent: 6011710 (2000-01-01), Wiggers
patent: 6140850 (2000-10-01), Inoue
patent: 6222389 (2001-04-01), Williams
patent: 6297663 (2001-10-01), Matsuoka et al.
patent: 6369605 (2002-04-01), Bonella et al.
patent: 6434647 (2002-08-01), Bittner, Jr.
patent: 6531901 (2003-03-01), Kamiya
patent: 6603323 (2003-08-01), Miller et al.
patent: 2001/0035768 (2001-11-01), Garlepp et al.
patent: 0674274 (1995-09-01), None
H. Bogenrieder, “Common Bosch Siemens Temic Bus Description, Rev. 2.00”, (Apr. 24, 2001) (see, e.g., par. 2.5.1; Fig. 12).
SFF Committee, “SFF-8046 Specification for 80-pin SCA-2 Connector for SCSI Disk Drives—Rev. 2.7”, Oct. 3, 1996.
SFF Committee, “SFF-8410 Specification for HSS Copper Testing and Performance Requirements-Rev. 16.1”, Mar. 20, 2000.
deBlanc James J.
Haynie Carl R.
White James L.
Hewlett--Packard Development Company, L.P.
Lee Christopher E.
Rinehart Mark H.
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