Fault tolerant asynchronous circuits

Details Fault tolerant asynchronous circuits Fault tolerant asynchronous circuits

2011-08-23

2011-08-23

Mai, Son L (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C326S009000, C326S012000

Reexamination Certificate

active

08004877

ABSTRACT:
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.

REFERENCES:
patent: 6094385 (2000-07-01), Trimberger
patent: 6301655 (2001-10-01), Manohar et al.
patent: 6320418 (2001-11-01), Fujii et al.
patent: 6381692 (2002-04-01), Martin et al.
patent: 6614257 (2003-09-01), Knowles
patent: 6658550 (2003-12-01), Martin
patent: 6690203 (2004-02-01), Nystrom et al.
patent: 6958627 (2005-10-01), Singh et al.
patent: 7036059 (2006-04-01), Carmichael et al.
patent: 7050324 (2006-05-01), Cummings et al.
patent: 7157934 (2007-01-01), Teifel
patent: 7283409 (2007-10-01), Voogel et al.
patent: 7283557 (2007-10-01), Cummings et al.
patent: 7301362 (2007-11-01), Jang et al.
patent: 7307450 (2007-12-01), Liang et al.
patent: 7345511 (2008-03-01), Morgenshtein et al.
patent: 7504851 (2009-03-01), Manohar et al.
patent: 7505304 (2009-03-01), Manohar et al.
patent: 7721183 (2010-05-01), Martin et al.
patent: 2002/0156995 (2002-10-01), Martin et al.
patent: 2002/0166003 (2002-11-01), Nystrom et al.
patent: 2003/0146075 (2003-08-01), Cummings et al.
patent: 2004/0130349 (2004-07-01), Morgenshtein et al.
patent: 2004/0151209 (2004-08-01), Cummings et al.
patent: 2006/0075210 (2006-04-01), Manohar et al.
patent: 2006/0090099 (2006-04-01), Martin et al.
patent: 2006/0233006 (2006-10-01), Fant
patent: 2007/0016823 (2007-01-01), Jang et al.
patent: 2007/0200608 (2007-08-01), Fang et al.
patent: 2007/0253240 (2007-11-01), Manohar et al.
patent: 2007/0256038 (2007-11-01), Manohar
patent: 2007/0262786 (2007-11-01), Manohar et al.
patent: 2009/0027078 (2009-01-01), Manohar et al.
patent: 2010/0207658 (2010-08-01), Manohar et al.
patent: WO-2007127917 (2007-11-01), None
patent: WO-2007127917 (2007-11-01), None
“U.S. Appl. No. 11/740,168 Notice of Allowance mailed Oct. 30, 2008”, 5 pgs.
“U.S. Appl. No. 11/740,168 Response filed Oct. 2, 2008 to Non-Final Office Action mailed Jun. 16, 2008”, 6 pgs.
“U.S. Appl. No. 11/740,168, Non-Final Office Action mailed Jun. 16, 2008”, 6 pgs.
“U.S. Appl. No. 11/740,180 Response filed May 30, 2008 to Non-Final Office Action mailed Mar. 14, 2008”, 8 pgs.
“U.S. Appl. No. 11/740,180 Notice of Allowance mailed on Nov. 7, 2008”, 12 pgs.
“U.S. Appl. No. 11/740,180 Non-Final Office Action mailed Mar. 14, 2008”, 10 Pgs.
“International Application Serial No. PCT/US2007/067622, International Search Report mailed Jun. 5, 2008”, 6 pgs.
“International Application Serial No. PCT/US2007/067622, Written Opinion mailed Jun. 5, 2008”, 5 pgs.
“U.S. Appl. No. 11/740,180, Notice of Allowance mailed Jul. 21, 2008”, 12 pgs.
Jang, Wonjin, et al., “SEU-tolerant QDI circuits—quasi delay-insensitive asynchronous circuits”,Proceedings—11th IEEE International Symposium on Asynchronous Circuits and Systems, 2005. ASYNC 2005., Dept. of Computer Science, California Institute of Technology, Pasadena, CA. This paper appears in: Asynchronous Circuits and Systems, 2005. ASYNC 2005. Proceedings. 11th IEEE International Symposium on, (Mar. 14-15, 2005), 156-165.
“U.S. Appl. No. 12/240,430, Notice of Allowance mailed Feb. 8, 2010”, 9 pgs.
“U.S. Appl. No. 12/240,430, Response filed Dec. 30, 2009 to Non Final Office Action mailed Oct. 1, 2009”, 12 pgs.
“Korean Application Serial No. 10-2008-7029014, Office Action mailed Sep. 3, 2010”, 5 Pgs.
“Korean Application Serial No. 10-2008-7029014, Office Action Response mailed Nov. 3, 2010”, 32 Pgs.
Gary, K M, et al., “Fault-Tolerant Asynchronous Sequential Machines”, IEEE transaction on computers, (Jul. 7, 1974), 651-657.
Mercer, E. G, et al., “Stochastic cycle period analysis in timed circuits”, The 2000 IEEE International Symposium on Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. vol. 2, (2000), 172-175.
Mercer, Eric, et al., “Stochastic cycle period analysis in timed circuits”, University of Utah Masters Thesis, Electrical Engineering Department, University of Utah, (May 1999), 78 pgs.
Peng, S., et al., “Automated Synthesis for Asynchronic FPGAs”, Symposium on Field Programmable Gate Arrays (FPGA '05), (2005), 11 pgs.
Teifel, John, et al., “Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis”, In 10th Int'l Symposium on Advanced Research in In Asynchronous Circuits and Systems, pp. 17-27, Computer Systems Laboratory, Cornell University, Ithaca, NY, (Apr. 2004), 11 pgs.
“U.S. Appl. No. 12/768,045, Non Final Office Action mailed Apr. 27, 2011”, 10 pgs.

Affiliated with

Also associated with

Rating

Fault tolerant asynchronous circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fault tolerant asynchronous circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fault tolerant asynchronous circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2740625