Fault tolerant and gate circuit

Details Fault tolerant and gate circuit Fault tolerant and gate circuit

1994-12-22

1995-10-10

Westin, Edward P.

Electronic digital logic circuitry

Reliability

Redundant

326104, H03K 19003

Patent

active

054574030

ABSTRACT:
A k-fault tolerant AND gate circuit comprises k+1 levels and the input level comprises k+1 AND gates. Embodiments provide intermediate levels arranged for providing a two-fault tolerant AND gate circuit and a four-fault tolerant AND gate circuit, respectively.

REFERENCES:
patent: 2942193 (1960-06-01), Tryon
patent: 3134032 (1964-05-01), Mann
patent: 3201701 (1965-08-01), Maitra
patent: 3543048 (1970-11-01), Klaschka
"Digital Design, Principles and Practices" by John F. Wakerly .COPYRGT. 1989 by John F. Wakerly, pp. 129-130.
D. Kleitman et al, "On the Design of Reliable Boolean Circuits that Contain Partially Unreliable Gates" Proceedings from 35th Ann. Symp. on Foundations of Computer Sci., Nov. 20-22, 1994, pp. 332-346.

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