Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-02-27
2007-02-27
Baderman, Scott (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S010000, C712S012000, C712S015000
Reexamination Certificate
active
10469002
ABSTRACT:
A multiprocessor, parallel computer is made tolerant to hardware failures by providing extra groups of redundant standby processors and by designing the system so that these extra groups of processors can be swapped with any group which experiences a hardware failure. This swapping can be under software control, thereby permitting the entire computer to sustain a hardware failure but, after swapping in the standby processors, to still appear to software as a pristine, fully functioning system.
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Chen Dong
Coteus Paul W.
Gara Alan G.
Takken Todd E.
Baderman Scott
Morris, Esq. Daniel P.
Schell Joseph
Scully , Scott, Murphy & Presser, P.C.
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