Fault simulator for verifying reliability of test pattern

Details Fault simulator for verifying reliability of test pattern Fault simulator for verifying reliability of test pattern

2006-08-22

2006-08-22

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S033000, C714S741000

Reexamination Certificate

active

07096384

ABSTRACT:
A fault simulator includes a circuit identifying section that selects, as fault generation points, circuit components subjected to a simulation from timing simulation results obtained by a static timing simulation of an LSI circuit; a fault value computing section that generates delay faults corresponding to the fault generation points using information about delay time and timing of signal transmission in the timing simulation result; and a fault simulating section that performs, by using a test pattern of the simulation, a logic simulation of a normal circuit of the LSI circuit and that of a faulty circuit where the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from the compared results of both the logic simulations. The fault simulator can reduce the time of the fault simulation.

REFERENCES:
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patent: 6490702 (2002-12-01), Song et al.
patent: 6708139 (2004-03-01), Rearick et al.
patent: 2003/0149916 (2003-08-01), Ohtake et al.
patent: 2003/0188246 (2003-10-01), Rearick et al.
patent: 2005/0149790 (2005-07-01), Yoshida et al.
patent: 9-54136 (1997-02-01), None

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