Fault simulation using dynamically alterable behavioral models

Details Fault simulation using dynamically alterable behavioral models Fault simulation using dynamically alterable behavioral models

1998-02-27

2001-01-02

Teska, Kevin J. (Department: 2763)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C714S025000

Utility Patent

active

06170078

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to the fault testing of electrical circuits, and, more particularly, to a system and method for simulating faults having dynamically alterable behavioral models of embedded circuits.
BACKGROUND OF THE INVENTION
Electrical circuits, and digital circuits in particular, must be rigorously tested prior to being brought to market. Such testing insures a level of quality and functionality in a proposed circuit design before large amounts of time, money, and other resources are expended in manufacturing the product. Such testing further insures a level of quality and functionality during the manufacturing process where the circuit design actually implemented may be tested. Accordingly, devices known as Fault Simulation Tools have been developed to allow circuit designers to verify and test their designs both prior to prototyping and during manufacturing. An example of such circuit designs include embedded memories (i.e., instruction cache, data cache, etc.) within microprocessors such as, for example, the Intel PENTIUM® processor. The circuit designs of these embedded memories require extensive testing in order to ensure proper operation of the processor. Otherwise, data may be erroneously modified and the processor may work improperly or may not work at all.
One approach employing fault simulation tools entails the development of a gate-level fault model which is composed of simpler fault model elements. However, this approach is non-trivial and for large memories consumes large amounts of memory or circuitry in the fault simulation tool. Additionally, the types of detectable faults are limited to the fault models supported by the fault simulation tool. Other approaches employing fault simulation tools only allow the simulation of faults at the perimeter of the fault model, thus sacrificing faults internal to the model. Accordingly, a system and method which overcomes these disadvantages is desired.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a method for fault simulation testing of circuits is provided. The method includes the steps of: providing a behavioral model of a circuit to be tested, wherein the behavioral model comprises at least one fault bus line; applying fault simulation test data to the behavioral model; and recording the behavior of the behavioral model to determine whether a defect is present.
The fault simulation tool applies mapping fault and test pattern information to the behavioral model. The behavioral model associates the mapping fault values on the fault bus with a predetermined behavior, which may be a defect or other condition, in the behavior model. The mapping fault information applied to the fault bus includes stuck-at-0 and stuck-at-1 faults or defects. A stuck-at-0 defect is defined as maintaining a particular bit at a zero value regardless what value is being written to or read from the bit. Similarly, a stuck-at-1 maintains a particular bit value at one. Once the predetermined behavior is known, the behavioral model acts accordingly, generating data based on the predetermined behavior. The data is read by the fault simulation tool and analyzed to determine whether the fault simulation test parameter data (sometimes hereinafter referred to as “test pattern”) detected the predetermined behavior or defect. Such analysis is facilitated by applying the mapping fault information and test pattern information to at least one faulty behavioral model and one fault-free behavioral model with a comparison of the results.
It is therefore an advantage of the present invention to provide a system and method for the fault testing of circuits with behavioral models that allow the representation of internal circuit faults.
It is a further advantage of this invention to provide a system and method for conveying unique defect information to a circuit behavioral mode.
It is still further an advantage of the present invention to extend the fault model testing capabilities of simple fault model testing tools to any fault capable of being behaviorally modeled.


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