Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2001-06-13
2002-10-08
Thompson, Craig (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C716S030000
Reexamination Certificate
active
06461882
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a fault simulation method and a fault simulator which prepare a fault list occurring in a semiconductor integrated circuit which can be detected with a test pattern sequence.
According to a conventional practice, a fault simulation of a semiconductor integrated circuit comprises assuming a fault within the integrated circuit, calculating an output value from an output terminal in response to a given test pattern by a logic simulation, determining a fault in which a change occurs as compared with an output value of a fault-free arrangement, assembling such results into a table of correspondence between assumed faults and input/output logic values, which is commonly referred to as a fault dictionary, thus preparing a fault list which can be detected with individual test patterns. When testing a semiconductor integrated circuit, each test pattern is applied to the input of the semiconductor integrated circuit, and the resulting output value and the input are used in making a reference to the fault dictionary in order to estimate whether or not there is a fault in the integrated circuit or/and where in the integrated circuit the fault is located.
In order to accommodate for a fault which does not give rise to a wrong logic such as a short-circuit fault or a current leak fault, there is proposed a fault simulation method which combines the logic simulation with IDDQ (quiescent power supply current) testing technique. According to this method, a logic signal value on a signal line within the integrated circuit which would occur in response to a test pattern is calculated by the logic simulation. By assuming faults within the integrated circuit to enumerate a variety of faults which satisfy requirements for the occurrence of an abnormality in IDDQ, a list of detectable faults is prepared. When a test pattern is input to the integrated circuit, each signal line in the integrated circuit normally assumes either “0” or “1” logic value. Accordingly, if a short-circuit fault occurs between a signal line having a logic value of “0” and a signal line having a logic value of “1” in the integrated circuit in response to the application of the test patter, an IDDQ abnormality occurs in the integrated circuit. In this manner, for any combination of a signal line having a logic value of “0” and a signal line having a logic value of “1” in the integrated circuit, a short-circuit fault which occurs between the both kinds of signal lines can be detected by the IDDQ testing technique in response to the input test pattern. When these short-circuit faults are enumerated, a fault list which can be detected with the IDDQ testing technique can be prepared.
However, the fault simulation method which employs the logic simulation can only deal with a fault model in which a signal line is fixed to a given state (either “0” or “1”, or a single stuck-at fault, namely stuck-at 0 or stuck-at 1). This prevents a sensitive simulation of a multiple stuck-at fault in which a plurality of signal lines are fixed to either “0” or “1”,a delay fault, a short-circuit fault between signal lines or the like. Accordingly, this fault simulation method cannot prepare a list of detectable faults for these faults.
Another difficulty of the fault simulation method which combines the logic simulation with the IDDQ testing technique is the fact that it is incapable of preparing a list of detectable faults for those faults related to a transient phenomenon of a semiconductor integrated circuit such as a delay fault or an open fault which influences upon a delay time or an abnormality in a local or global process parameter (such as sheet resistance, an oxide film thickness of the like) for example, inasmuch as the IDDQ testing technique is directed to determining a power supply current in the stable condition of the semiconductor integrated circuit or is principally directed to short-circuit faults in the circuit.
Accordingly, there is a need for a fault simulation method capable of preparing a fault list which are detectable with a test pattern sequence for faults including a delay fault, an open fault or a parametric abnormality fault in an integrated circuit.
It is an object of the invention to provide a fault simulation method and a fault simulator capable of preparing a fault list which are detectable with test pattern sequence for delay faults, open faults and parametric abnormality faults in a semiconductor integrated circuit, by using the IDDT (transient power supply current) testing technique which affords a high level of observability and capable of testing transient phenomena in the circuit in combination with a transition simulation.
DISCLOSURE OF THE INVENTION
According to the present invention, there is provided a method of preparing a fault list which are detectable with input test pattern sequence, comprising a step of deriving a test pattern sequence formed by two or more test patterns and which is to be applied to a semiconductor integrated circuit under test, a step of performing a transition simulation of an operation of the semiconductor integrated circuit under test when each test pattern in the derived test pattern sequence is applied thereto to calculate a train of transition signal values occurring on signal lines within the semiconductor integrated circuit under test, and a step of preparing a fault list which can be detected by the transient power supply current testing which uses the test pattern sequence, by utilizing the train of transition signal values on signal lines which are calculated by the transition simulation.
With this method, it is possible to prepare a fault list which are detectable by the transient power supply current testing which uses given test patterns, for those faults which have been difficult to detect in the prior art, namely, delay faults and open faults which give rise to delay faults, thus allowing a substantial improvement in the efficiency of testing against delay faults and open faults.
In one form of the step of preparing the fault list, the fault list is prepared in unit of a delay fault of a logic gate.
In another form of the step of preparing the fault list, the fault list is prepared in unit of an open fault in a signal line.
In a further form of the step of preparing the fault list, the fault list is prepared in unit of a path delay fault on a signal transmission path.
The present invention also provides a fault simulator which prepares a fault list which are detectable with an input test pattern sequence, comprising a test pattern sequence selector for deriving a test pattern sequence formed by two or more test patterns and which is to be applied to a semiconductor integrated circuit under test, a transition simulator which receives the derived test pattern sequence and performs a transition simulation of the operation of the semiconductor integrated circuit under test when each test pattern of the sequence is input thereto to calculate a train of transition signal values occurring on signal lines within the semiconductor integrated circuit under test, and a fault list preparing unit for preparing a fault list which are detectable by the transient power supply current testing which uses the test pattern sequence, by utilizing the train of transition signal values on signal lines which are calculated by the transition simulator.
The fault simulator allows a fault list which are detectable by the transient power supply current testing which uses certain test pattern to be prepared, for a delay fault or an open fault which leads to a delay fault, either of which has been difficult in the prior art to detect, thus permitting the testing efficiency for the delay faults and the open faults to be significantly improved.
In the description to follow, the principle of the present invention will be described in terms of a CMOS integrated circuit which is a most common semiconductor integrated circuit.
Transient current of CMOS logic gate
FIG. 1
shows a transient response of a CMOS inverter shown in
FIGS. 1
c
and
d
. The
Ishida Masahiro
Yamaguchi Takahiro
Advantest Corporation
Gallagher & Lathrop
Lathrop, Esq. David N.
Thompson Craig
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