Fault repair controller for redundant memory integrated...

Details Fault repair controller for redundant memory integrated... Fault repair controller for redundant memory integrated...

2005-08-09

2005-08-09

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S723000

Reexamination Certificate

active

06928591

ABSTRACT:
A controller for repairing a redundant memory circuit includes a fault storage matrix for mapping a repair solution, a plurality of registers for storing row and column coordinates of the repair solution, and a repair solution calculator coupled to the plurality of registers and the fault storage matrix for receiving an x-coordinate and a y-coordinate of a defective memory cell in the redundant memory circuit and for determining whether a repair solution may be found from the fault storage matrix.

REFERENCES:
patent: 4751656 (1988-06-01), Conti et al.
patent: 6026505 (2000-02-01), Hedberg et al.
patent: 6795942 (2004-09-01), Schwarz
patent: 2003/0101389 (2003-05-01), Rieger
John R. Day, “A Fault-Driven, Comprehensive Redundancy Algorithm”, International Test Conference 1984, Jun. 1985, pps. 35-44.
Wei Kang Huang et al., “New Approaches for the Repairs of Memories with Redundancy by Row/Column Deletion for Yield Enhancement”, IEEE Transactions On Computer-Aided Design, vol. 9, No. 3, Mar. 1990, pps. 323-328.

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