Fault processing for direct memory access address translation

Details Fault processing for direct memory access address translation Fault processing for direct memory access address translation

2008-03-04

2008-03-04

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S100000, C711S200000

Reexamination Certificate

active

07340582

ABSTRACT:
An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.

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