Fault isolation in a programmable logic device

Details Fault isolation in a programmable logic device Fault isolation in a programmable logic device

2007-06-19

2007-06-19

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

10959389

ABSTRACT:
Identification of a faulty net in a design implemented on a programmable logic device (PLD). In one approach, configuration data is generated to implement a duplicate circuit of a failing sub-circuit in the design. The PLD is configured with the configuration data that implements the failing sub-circuit and the duplicate circuit, and at least one set of input signals is applied to the sub-circuit and the duplicate circuit. A signal from each net in the sub-circuit is compared on the PLD to a corresponding net in the duplicate circuit. In response to the signal from the net in the sub-circuit being unequal to a signal from the corresponding net in the duplicate circuit, the net in the sub-circuit is identified as faulty.

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