Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
1999-09-29
2003-02-11
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S724000, C714S023000, C714S043000, C714S056000, C324S512000, C711S114000
Reexamination Certificate
active
06519739
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
As is known in the art, large mainframe computer systems require large capacity data storage systems. These large main frame computer systems generally include data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the main frame computer system are coupled together through an interface. The interface includes CPU, or “front end”, controllers (or directors) and “back end” disk controllers (or directors). The interface operates the controllers (or directors) in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. No. 5,206,939, entitled “System and Method for Disk Mapping and Data Retrieval”, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. Patent, the interface may also include, in addition to the CPU controllers (or directors) and disk controllers (or directors), addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the main frame computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the main frame computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a pair of buses. One set of the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set of the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both buses. Each one of the buses provides data, address and control information.
SUMMARY OF THE INVENTION
In accordance with the present invention, a circuit is provided for detecting a fault on a bi-directional data line. The circuit includes: an input/output terminal connected to one end of the bi-directional line; a data receiver having an input coupled to a second end of the bi-directional line for receiving data on the terminal; a data driver having an output coupled to second end of the bi-directional line for producing data on the terminal; an XOR gate having a pair of inputs, one being coupled to an output of the data receiver and the other being coupled to an input of the data driver, for determining whether data produced by the data driver is received by the data receiver.
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Co-Pending patent application Ser. No. 09/408,058, filed Sep. 29, 1999 and Assigned to Art Unit 2818.
Co-Pending patent application Ser. No. 09/408,430 filed Sep. 29, 1999 and Assigned to Art Unit 2751.
Co-Pending patent application Ser. No. 09/408,807 filed Sep. 29, 1999 and Assigned to Art Unit 2751.
Co-Pending patent application Ser. No. 09/408,811 filed Sep. 29, 1999 and Assigned to Art Unit 2751.
Co-Pending patent application Ser. No. 09/408,429 filed Sep. 29, 1999 and Assigned to Art Unit 2851.
Daly, Crowley & Mofford LLP
EMC Corporation
Moise Emmanuel L.
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