Fault detection in memory refreshing system

Details Fault detection in memory refreshing system Fault detection in memory refreshing system

1988-10-28

1990-06-12

Gossage, Glenn A.

Static information storage and retrieval

Read/write circuit

Data refresh

36523002, 365236, 365200, 371 681, 371 82, G11C 700, G11C 2900

Patent

active

049339087

ABSTRACT:
A dynamic random access memory (DRAM) memory refreshing scheme utilizes at least two separate refresh channels. Each of the channels consists of a pair of identical counters which are coupled through two different types of timing chains. One of the timing chains is associated with one of the counters and generates a refresh request signal, while the other timing channel generates a refresh error signal. As long as the refresh error signal matches the refresh request signal, no error is present, and a validated refresh request signal will be generated from that timing channel and supplied to an OR gate to refresh all of the memory banks for the memory. Whenever a mismatch occurs between the refresh error signal and the refresh request for one of the refresh channels, the validated refresh request signal for that channel will be inoperable, and continued refreshing operation of the memory depends on the supply of the validated refresh request signals through the other channel in which the refresh request signal and the refresh error signals still match.

REFERENCES:
patent: 3944800 (1976-03-01), Beck et al.
patent: 4185323 (1980-01-01), Johnson et al.
patent: 4701843 (1987-10-01), Cohen

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