Fault detection for entire wafer stress test

Details Fault detection for entire wafer stress test Fault detection for entire wafer stress test

1995-07-31

1997-04-08

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Testing

365226, 257 48, G11C 2900

Patent

active

056194625

ABSTRACT:
A circuit and related method are provided for parallel stressing of a plurality of memory circuits integrated on dies on a silicon wafer. On each die, a test mode control circuit, having a first and a second test mode control inputs, and a test enable circuit, having a first and a second test enable inputs, are used to enable test operation mode and to force outputs of address buffers, data buffers and other signal buffers, like chip-enable or write buffers, to predetermined logic values so that all row and column decoders are selected and predetermined data is written into the memory cells. Contemporaneously are also exercised entire paths of buffers. The silicon wafer is then heated and maintained at an elevated temperature for a desired time, and then cooled down. In this way it is possible to stress test for ionic contamination, trap sites and weak oxides a plurality of integrated circuits on the same wafer in a short time, requiring only a limited number of test signals. During the test the current consumed by each die is monitored and, if a high current is consumed by one die, that die is isolated from the array of dies by controlling the test enable signals present in each row and column of the array. This circuit allows a parallel testing of a plurality of integrated circuits on a single wafer, reduces dramatically test times and avoids consequent burn in of packaged devices.

REFERENCES:
patent: 5053700 (1991-10-01), Parrish
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5241266 (1993-08-01), Ahmad et al.
patent: 5339277 (1994-08-01), McClure
patent: 5341336 (1994-08-01), McClure
patent: 5446395 (1995-08-01), Goto

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