Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-05-15
1998-11-17
Hua, Ly
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
39518318, 39518306, 711100, G06F 1200, G06F 1300
Patent
active
058388958
ABSTRACT:
The present invention relates to a fault detection and automatic recovery apparatus of write-read pointers in FIFO. While storing effective data in a register in writing performance, the apparatus does not unconditionally enable a FULL.sub.-- FLAG signal allotted to the register but confirms the relation of write-read pointers at that time and the EMPTY.sub.-- FLAG signal of a register at which the read pointer is situated and detects the error of FIFO. By selectively enabling the FULL.sub.-- FLAG signal of the register according to the result of detection, it automatically restores the FIFO functions without unnecessary re-initialization or the discontinuation of data transmission attributable thereto.
REFERENCES:
patent: 4949301 (1990-08-01), Joshi et al.
patent: 5046000 (1991-09-01), Hsu
patent: 5404332 (1995-04-01), Sato et al.
patent: 5426756 (1995-06-01), Shyi et al.
Jung Hee-Bum
Kim Seong-Do
Song Won-Chul
Electronics and Telecommunications Research Institute
Hua Ly
Korea Telecommunication Authority
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