Fastplace method for integrated circuit design

Details Fastplace method for integrated circuit design Fastplace method for integrated circuit design

2007-09-04

2007-09-04

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

11102381

ABSTRACT:
A method for efficient analytical placement of standard cell designs includes obtaining a placement of cells using a wirelength objective function, modifying the placement of cells by cell shifting to redistribute cells to thereby reduce cell overlap, and refining the placement of cells to thereby reduce wirelength using a half-perimeter bounding rectangle-measure. Preferably the wirelength the wirelength objective function is a quadratic objective function which is solved using a hybrid net model. The hybrid net model preferably uses a clique model for two-pin and three-pin nets and a star model for nets having at least four pins. The use of the hybrid net model reduces a number of non-zero entries in a connectivity matrix.

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