Fast turn-off slow turn-on arbitrator for reducing tri-state...

Details Fast turn-off slow turn-on arbitrator for reducing tri-state... Fast turn-off slow turn-on arbitrator for reducing tri-state...

2007-04-10

2007-04-10

Rinehart, Mark H. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S113000, C710S114000

Reexamination Certificate

active

10060454

ABSTRACT:
A bus arbitrator for use in a shared bus system in which N bus devices request access to a shared bus. The bus arbitrator slowly activates and rapidly de-activates tristate line drivers coupled to the shared bus. The bus arbitrator comprises: 1) an input interface for receiving a first bus access request signal from a first bus device; 2) a delay circuit that receives the first bus access request signal from the input interface and generates a time-delayed first bus access request signal; and 3) a comparator circuit that receives the first bus access request signal from the input interface and the time-delayed first bus access request signal from the delay circuit and generates a line driver enable signal only if both of the first bus access request signal and the time-delayed first bus access request signal are enabled. The comparator circuit disables the line driver enable signal if either of the first bus access request signal or the time-delayed first bus access request signal is disabled.

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Hill, Frederick J. et al. Computer Aided Logical Design With Emphasis on VLSI. Fourth Edition. 1993. John Wiley & Sons, Inc. ISBN 0-471-57527-5. pp. 54-57.

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