Fast transmission line implemented with receiver, driver, termin

Details Fast transmission line implemented with receiver, driver, termin Fast transmission line implemented with receiver, driver, termin

1996-11-12

1998-06-16

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

333 32, H03K 1716

Patent

active

057676950

ABSTRACT:
A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself. Each of the intra-block transmission line is provided with a resistance element having a resistance equal to or close to a value derived by subtracting a half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

REFERENCES:
patent: 3694665 (1972-09-01), Belluche
patent: 3832575 (1974-08-01), Dasgupta et al.
patent: 4987318 (1991-01-01), Burke et al.
patent: 5003467 (1991-03-01), Donaldson et al.
patent: 5019728 (1991-05-01), Sanwo et al.
patent: 5046072 (1991-09-01), Shimizu et al.
patent: 5227677 (1993-07-01), Furman
"New I/O Proposal", Fujitsu, JEDEC JC16, San Diego, CA, Dec. 15, 1993, pp. 1-12.

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