Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1995-06-06
1997-01-14
Safourek, Benedict V.
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
327156, 327160, H03D 324
Patent
active
055947638
ABSTRACT:
A digital phase-locked loop for receiving an encoded stream of data and generating a receive clock signal therefrom is provided with a counter, such as a down counter, having an adjustable start count value. An edge detector detects the rising and falling edges within a stream of data. The detection of an edge causes the counter to start counting from the start count value towards a terminal value. A receive clock generator is provided that generates a receive clock signal, the receive clock generator being responsive to the counter reaching at least a first predetermined value to change a level of the receive clock signal. The use of a down counter that is loaded with a start count value upon the detection of an edge provides fast re-synchronization when an edge has been missed, while providing accurate recovery of the clock from the encoded stream of data.
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Cirrus Logic Inc.
Loomis Paul
Safourek Benedict V.
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