Fast static random access memory

Details Fast static random access memory Fast static random access memory

1990-10-22

1993-07-13

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Signals

36518905, G11C 1300

Patent

active

052279987

ABSTRACT:
A static RAM has for each row of cells a bit line and an inverted bit line. For allowing the current data being driven to each cell to be instantaneously stopped and for allowing the (inverted) bit line to go back to a safe non-writing condition two resettable delay chains are provided between a buffering element that has mutually logically inverse data outputs. Each chain has a first sequence of alternating inverter gate series feeding a second sequence of one or more inverters. At the end of a write cycle the gates are reset in parallel, thus shortening the delay to about that of the second sequence only. In this way operating margins are retained.

REFERENCES:
patent: 4567579 (1986-01-01), Patel et al.
patent: 4586167 (1986-04-01), Fujishima et al.

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