Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-06-13
2002-05-21
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S026000
Reexamination Certificate
active
06392441
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to driver circuits. More particularly, the present invention relates to a transmission line driver circuit that minimizes ringing effects while providing a fast output response.
2. Relevant Background
Integrated circuits (ICs) comprise thousands or millions of individual devices interconnected to provide desired functionality. Significant effort is expended to improve processing techniques so as to reduce the size of each individual device in order to provide greater functionality and higher operating speed at reduced cost. Despite advances in integration, complex chips usually require multiple ICs coupled together in modules, circuit boards and the like. In order to function together, data must be transmitted rapidly between ICs. Currently, chip-to-chip transmission speeds are a fraction of the on-chip transmission speeds. Inter-chip data transmission is a significant bottleneck limiting overall system performance.
The physical distance between the input and output devices makes “transmission-line” effects degrade the transmitted signal. Transmission-line effects are due to the impedance of the signal conductor that connect the devices. As the devices are spaced further apart, problems with transmission line effects become more pronounced. Moreover, as bus clock speeds increase, transmission line effects are significant for even relatively short conductor lines. For some types of integrated circuits, such as the fastest ECL chips, transmission-line effects have prevented signal runs from exceeding one inch. These limitations significantly constrain the complexity and performance that can be integrated on a circuit board.
One technique of addressing the transmission-line effects is to utilize a driver to overcome the signal run's impedance and rapidly adjust the signal that is translated to signal bus. Although a conventional driver may be utilized when the signal run has a constant impedance, many factors may cause the impedance to change. When the impedance is high, such as under a maximum load with low source voltage and high temperature, the output signal may have an excessive response to transition from a voltage associated with high logic or power supply voltage (VDD) to a voltage associated with low logic, such as common potential or ground (VSS). Conversely, when there is a minimum load with high source voltage and low temperature, the output signal may have excessive ringing which is seen as noise in the input device.
It would be desirable to have a transmission line driver circuit that minimizes or eliminates transmission line ringing effects on a chip and also provide a fast initial response for a large range of bus impedance without the use of additional external circuitry. Further, a need exists for a driver circuit that readily adapts to the varying load conditions found in practical systems.
SUMMARY OF THE INVENTION
The present invention provides fast initial response times for a large range of bus impedances while limiting ringing caused by aggressively driving the output. The present invention involves the use of a plurality of delay circuits to synchronize the activation of a plurality of output driver transistors. An input signal is received and propagates through each of the delays in series, and each delay is connected to at least one threshold voltage drop or inverter module. Each of the threshold voltage drops and inverter modules are, in turn, connected to a driver that is in turn connected to the output bus. In this way, the signal is driven by progressively stronger devices.
The invention integrates a feedback signal into a fast response circuit. This feedback signal measures an output signal at a predetermined time after a first weak threshold voltage drop is activated to determine whether the output signal is being driven to ground (GND) at a satisfactory rate. When the output signal falls below a predetermined voltage within a predetermined time, a strong inverter activates and causes the output signal to be driven to ground. If the output signal is not below the predetermined voltage at the predetermined time, the strong inverter activates automatically. By delaying the activation of the strong inverter until either the output signal is sufficiently low or the predetermined time has elapsed, the ringing effects would not exist since the activation of the strong inverter is designed to conduct when the output is at approximately 25% VDD.
According to the present invention, an input signal is received and propagates through each of the delays in series, and each delay is connected to at least one threshold voltage drop or inverter module. Each of the threshold voltage drops and inverter modules are, in turn, connected to a driver. The driver is, in turn, connected to the output bus. In one embodiment, as the input signal propagates through each delay, an output device stronger than the previous output device is activated. This result may be achieved by using devices that result in different currents and voltages being applied to the output bus. In one embodiment, devices ranging in strength and voltage from a weak threshold voltage drop to a semi-weak inverter may be used. In this way, the driver circuit both drives the output signal quickly to low when there is high impedance and avoids ringing when there is low impedance.
In another aspect, the present invention involves a digital logic circuit that can be used to activate a strong inverter. The digital logic circuit may be adaptive in that the strong inverter is selectively activated based upon feedback and the passage of a predetermined amount of time. For example, the digital logic circuit may receive a feedback signal from the output bus and a timing signal from the final delay. The digital logic circuit may be configured so that the strong inverter is fired either when the feedback signal drops below a predetermined threshold voltage or after a predetermined amount of time, whichever comes first. Once the first of these conditions is satisfied, the strong inverter is activated in order to “slam” the output signal to VSS. In one embodiment, the predetermined threshold is 25% of VDD.
In another aspect, the present invention involves a method for rapidly driving an output signal to a supply rail voltage (e.g., ground) without causing ringing under both high and low transmission line impedance conditions. Using a series of delays and a plurality of threshold voltage drop and inverter modules, an output signal is driven to ground with increasingly stronger modules. In a preferred embodiment, a strong inverter is activated after a predetermined amount of time to drive output signals to ground when there is a large impedance tied to the bus.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.
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Cho James H
Hogan & Hartson
Kubida William J.
Langley Stuart T.
Ramtron International Corporation
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