Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2006-11-08
2008-10-14
Kim, Hong (Department: 2185)
Static information storage and retrieval
Read/write circuit
Data refresh
C711S106000, C711S005000
Reexamination Certificate
active
07436728
ABSTRACT:
A method to manage fast random access of a DRAM memory is described. The method includes steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request and comparing the address of the bank concerned by a current request with the addresses of the N−1 banks previously requested. N is an integral number of cycles necessary for executing a request. If the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N−1 previous requests, then the method further includes steps of suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise the current request is executed.
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French Search Report from French Patent Application 01/01934, filed Feb. 13, 2001.
Bulone Joseph
Harrand Michel
Jorgenson Lisa K.
Kim Hong
Morris James H.
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
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