Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-10-29
2004-11-16
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S663000, C438S675000, C438S691000
Reexamination Certificate
active
06818548
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to manufacturing of microelectronic devices. In particular, the present invention relates to the using a rapid annealing process for suppressing hillock formation in copper-containing structures of a microelectronic device.
2. State of the Art
In the fabrication of microelectronic devices, integrated circuitry is formed in and on an active surface of a microelectronic die, typically doped monocrystalline silicon. A build-up layer is then formed on the microelectronic die active surface. This buildup layer consists of dielectric layers (called “interlayer dielectric layers” or, hereinafter, “ILD layers”) having conductive traces, such as bus lines, bit and word lines, logic interconnect lines and the like, extending on (approximately parallel to the microelectronic die active surface) and through each of the ILD layers in the build-up layer. This build-up layer results in a matrix of conductive traces to send and/or receive signals between components of internal integrated circuitry, and to send and/or receive signals between external electronic devices and the integrated circuitry of the microelectronic die. The build-up layers may also include conductive traces for power supply (source and ground), as well as passive components such as capacitors and resistors.
There is an on-going demand for higher performance and increased miniaturization of integrated circuit components within the microelectronic dice. As these goals are achieved, the geometry of microelectronic die integrated circuitry becomes smaller or is “scaled down”. As the geometry is scaled down, the properties of the conductive traces begin to dominate the overall speed of the integrated circuitry. In order to increase the speed and reliability of the conductive traces, the electronics industry has moved away from using aluminum to using copper or copper alloys as a preferred material for the conductive traces. Although generally more expensive than aluminum, copper has a lower resistivity (resulting in lower resistance-capacitance interconnect delay) and better electromigration characteristics than aluminum.
The preferred way to process copper-containing conductive traces is to etch a line trench in the ILD layer and/or etch a via hole though the ILD layer, deposit the copper-containing material to fill the trench or hole, and then polish it back to remove any excess copper-containing material. The resulting filled trench and/or via form the conductive trace. Forming the conductive trace by this method is called the damascene process. If a trench and an underlying via hole are filled simultaneously, it is known as a dual-damascene process.
One problem that can occur in the use of copper-containing materials is the formation of hillocks due to stresses built up in the conductive traces as a result of various processing steps in forming microelectronic device. Hillocks are spike-like projections that erupt and protrude from the conductive traces in response to compressive stresses which buildup in the conductive traces. The compressive stresses result because of the differing thermal coefficient of expansion between dielectric materials and metals (more than an order of magnitude in some cases). Upon thermal cycling from fabrication processes, metals, such as copper-containing material in a build-up layer, expand more than the dielectric materials (or even the microelectronic die). As a result, compressive stresses build in the conductive traces. If the compressive stresses become too large, the stresses are relieved by the growth of hillocks.
FIG. 11
illustrates exemplary problems with hillocks within a build-up layer
200
formed in a microelectronic die (not shown). The build-up layer
200
includes a first copper-containing structure
202
and a second copper-containing structure
204
formed in a first ILD layer
206
. Hillocks
210
erupting from the first copper-containing structure
202
can pierce through the second ILD layer
208
(covering the first ILD layer, the first copper-containing structure
202
and the second copper-containing structure
204
) and extend into structures in the second ILD layer.
FIG. 11
illustrates a passive structure as a capacitor
212
on electrical contact with a first conductive trace
214
formed in a third dielectric layer
216
. Hillock extending into a capacitor
212
shorts it and renders the capacitor inoperative (and perhaps the entire microelectronic die inoperative), as will be understood to those skilled in the art. Hillocks
220
erupting from the second copper-containing structure
204
can pierce through the second ILD layer and the third ILD layer to contact a second conductive trace
214
. Again, this results in a short therebetween rendering the elements and/or the entire microelectronic die inoperative. It is, of course, understood that the hillocks can extend through multiple ILD layers and may contact any structures within the build-up layer. It is further understood that the dimensions of the elements of
FIG. 11
are exaggerated to aid conceptual understanding.
In the fabrication of copper-containing conductive traces, electromigration reliability can be improved by annealing (i.e., heating) the traces. Annealing increases the grain size of the copper, thereby improving electromigration reliability. It has also been found that annealing can reduce the likelihood of hillock formation. Furthermore, various techniques such as coating the traces with metal alloys, oxidizing the top surface of the traces, and the like have also been used to reduce the likelihood of hillock formation.
Although there are methods of suppressing hillock formation in copper-containing conductive traces, improvements are always sought. Therefore, it would be advantageous to develop methods for fabricating copper-containing structures, such as conductive traces, which reduces or substantially eliminates hillock formation thereon.
REFERENCES:
patent: 6348410 (2002-02-01), Ngo et al.
patent: 6368948 (2002-04-01), Ngo et al.
patent: 6391777 (2002-05-01), Chen et al.
patent: 2002/0098710 (2002-07-01), Sandhu et al.
Chambers Stephen T.
Lavric Dan S.
Brewster William M.
Intel Corporation
Winkle Rob G.
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