Fast priority determination circuit with rotating priority

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

Reexamination Certificate

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Details

C711S212000, C711S220000, C710S040000, C710S107000

Reexamination Certificate

active

06915396

ABSTRACT:
The invention describes a system for and a method of creating and using dependencies to determine the order of servicing transaction requests in a multiple queue environment. When more than one outstanding transaction affects the same memory location, dependencies are established to ensure the correct sequencing of the competing transactions. In a preferred embodiment the dependency is configured to ensure that, as each request is inserted, other outstanding requests are checked to determine if the same memory location is accessed. If the same memory location is affected, a dependency is created which ensures the youngest queue entry which is present at the time the check is made occurs before the present outstanding request.

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patent: 6757768 (2004-06-01), Potter et al.
De Blasi, “Computer Architecture,” ISBN 0-201-41603-4 (Addison-Wesley, 1990), pp. 273-291.
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Tabak, “Advanced Microprocessors, ” ISBN 0-07-062807-6 (McGraw-Hill, 1991) pp. 244-248.
M. Papamarcos and J. Patel, “A Low Overhead Coherent Solution for Microprocessors with Private Cache Memories,” in Proceedings of the 11th International Symposium on Computer Architecture, IEEE, New York (1984), pp. 348-354.

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