Fast phase-frequency detector arrangement

Details Fast phase-frequency detector arrangement Fast phase-frequency detector arrangement

2011-06-07

2011-06-07

Corrielus, Jean B (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C327S157000, C327S159000

Reexamination Certificate

active

07957500

ABSTRACT:
A detector arrangement for detecting a frequency error between an input signal (DATA) and a reference signal. The detector arrangement comprising first latch circuitry (L1, L2) for sampling a quadrature component (CKQ) of the reference signal based on the input signal, to generate a first binary signal (PDQ); second latch circuitry (L3, L4) for sampling an in-phase component (CKI) of the reference signal based on the input signal, to-generate a second binary signal (PD I); third latch circuitry (L5) for sampling the first binary signal based on the second binary signal, to generate the frequency error signal (FD). The detector further comprising control circuitry (TS) for selectively suppressing operation of a charge pump (82) to which the first binary signal (PDQ) is supplied, in response to a control signal derived from the second binary signal.

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