Fast parallel calculation of cyclic redundancy checks

Details Fast parallel calculation of cyclic redundancy checks Fast parallel calculation of cyclic redundancy checks

2003-08-19

2008-01-15

Baker, Stephen M. (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S807000

Reexamination Certificate

active

07320101

ABSTRACT:
Circuits, methods, and apparatus for the fast parallel calculation of CRCs. One embodiment provides a feedforward path that combines common terms to simplify input logic. Common expressions that appear in multiple terms in the feedforward path are implemented using logic gates that are shared by the multiple terms, thereby reducing logic complexity, fan-out, and gate delay. Another embodiment provides a CRC logic architecture having a feedback path that is able to use more than one clock cycle in its computation.

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