Fast packet switch

Multiplex communications – Wide area network – Packet switching

Patent

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Details

370 94, H04Q 1104

Patent

active

044919450

ABSTRACT:
A communication method and packet switching system in which packets comprising logical addresses and voice/data information are communicated through the system by packet switching networks which are interconnected by high-speed digital trunks with each of the latter being directly terminated on both ends by trunk controllers. During initial call setup of a particular call, central processors associated with each network in the desired route store the necessary logical to physical address information in the controllers which perform all logical to physical address translations on packets of the call. Each network comprises stages of switching nodes which are responsive to the physical address associated with a packet by a controller to communicate this packet to a designated subsequent node. The nodes provide for variable packet buffering, packet address rotation techniques, and intranode and internode signaling protocols. Each packet has a field which is automatically updated by the controllers for accumulating the total time delay incurred by the packet in progressing through the networks. Each processor has the capability of doing fault detection and isolation on the associated network, trunks, and controllers by the transmission of a single test packet. The testing is done solely in response to the test packet and no preconditioning of controllers or networks is necessary.

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W. Neil et al., "Experimental Packet-Switched Service: Procedures and Protocols Part 1-Packet Formats, Facilities, and Switching", Post Office Electrical Engineers' Journal, vol. 67, pt. 4, pp. 232-239, Jan. 1975.
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1979 Aug.-Bolt, Beranek and Newman Inc., Report No. 4098, "Development of a Voice Funnel System", pp. III-29 through 76.
1981 IEEE International Conference on Communications, vol. 2, "The Use of Multi-Stage Switching Networks in the Design of Local Network Packet Switches", pp. 25.2.1-25.2.5.
1981 IEEE Transactions on Computers, vol. C-30, No. 4, Apr., 1981, "Analysis and Simulation of Buffered Detla Networks", pp. 273-282.

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