Fast Nor-Nor PLA operating from a single-phase clock

Details Fast Nor-Nor PLA operating from a single-phase clock Fast Nor-Nor PLA operating from a single-phase clock

1995-12-29

1999-09-28

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 45, 326 93, 326 98, H03K 19177

Patent

active

059594659

ABSTRACT:
A method is provided for operating a programmable logic array in an integrated circuit. Each stage of the circuit is enabled only during the time necessary for that stage to propagate an incoming signal. Enable signals are generated for the stages of the circuit, using a dummy circuit which replicates elements of the circuit in dimension, orientation and connectivity. These elements provide a delay path, such that an input signal applied coincidentally to the programmable logic array circuit and the dummy circuit produces outputs of the dummy circuit which define times for applying and removing the enable signals from stages of the programmable logic array circuit.

REFERENCES:
patent: 4751407 (1988-06-01), Powell
patent: 4760290 (1988-07-01), Martinez
patent: 4769562 (1988-09-01), Ghisio
patent: 4894564 (1990-01-01), Sakashita et al.
patent: 5083047 (1992-01-01), Horie et al.
patent: 5101122 (1992-03-01), Shinonara

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