Fast method for functional mapping to incomplete LUT pairs

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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C326S041000

Reexamination Certificate

active

11201565

ABSTRACT:
A configuration for a programmable device is determined to implement an incomplete function using at least two logic cells. Function inputs are partitioned into portions associated with first and second logic cells. The partitioning is screened to determine if it is potentially acceptable by determining if a portion of the function can be implemented using a complete look-up table. If the partitioning of the function inputs is potentially acceptable, the function inputs are assigned to the input ports of the logic cells. Variables are assigned to look-up table locations and a correspondence is determined between function input and output values, the variables, and the look-up table locations. Boolean tautology rules are applied to the correspondence to simplify the variables. If the simplified variables are consistent, a configuration is output that includes assignments of function inputs to input ports and look-up table data based on the simplified variables.

REFERENCES:
patent: 5990702 (1999-11-01), Agrawal et al.
patent: 2005/0040849 (2005-02-01), Pugh et al.
patent: 2006/0161725 (2006-07-01), Lee et al.

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