Fast memory device allowing suppression of peak value of operati

Details Fast memory device allowing suppression of peak value of operati Fast memory device allowing suppression of peak value of operati

1996-01-05

1998-03-10

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

365194, 365208, 36523003, G11C 700, G11C 702, G11C 800

Patent

active

057269432

ABSTRACT:
A memory cell array of a dynamic semiconductor memory device is divided into a plurality of memory cell blocks. A block selecting circuit selects and refreshes larger number of memory cell blocks in refreshing mode than the number of those selected during normal mode. Sense amplifiers in the memory cell blocks selected by the block selecting circuit are selectively driven with smaller driving force in refreshing mode than that in normal mode. More preferably the driving force is changed during the amplifying operation so as to achieve both the high sensitivity and the suppression of the peak value of the operational current.

REFERENCES:
patent: 4627033 (1986-12-01), Hyslop et al.
patent: 4943960 (1990-07-01), Komatsu et al.
patent: 5367493 (1994-11-01), Yamagata
patent: 5537359 (1996-07-01), Toda
patent: 5553028 (1996-09-01), McLaury
patent: 5559748 (1996-09-01), Numata et al.

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