Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2006-09-19
2006-09-19
Ray, Gopal C. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C717S136000, C717S139000, C711S118000, C711S203000
Reexamination Certificate
active
07111096
ABSTRACT:
Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Entries in the cache have a host instruction address and tags that may include a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction. The cache may be a software cache apportioned by software from the main processor memory or a hardware cache separate from main memory.
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Banning John
Choy Brian
Coon Brett
Gainer Patrick
Torvalds Linus
Ray Gopal C.
Transmeta Corporation
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