Fast locking CDR (clock and data recovery circuit) with high...

Details Fast locking CDR (clock and data recovery circuit) with high... Fast locking CDR (clock and data recovery circuit) with high...

2001-10-26

2003-04-08

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S094000, C326S009000

Reexamination Certificate

active

06545507

ABSTRACT:

TECHNICAL FIELD OF INVENTION
The present invention relates generally to serial data communication and transmission applications in the manufacture of integrated circuits needed as physical interface to any type of serial bus (in this example USB). More particularly, the present invention relates to clock and data recovery logic for a serial data stream, which supplies a sync lock within 1.5 bit times, insuring clock and data information is recovered in these applications. The CDR function is implemented as a plesiochronous technique with no feedback to a PLL. It also has no lock detection, nor loss of lock detection, nor loss of sync detection. In the intended application, those functions are integrated into the logic coupled to the recovered CLK and DATA.
BACKGROUND OF THE INVENTION
With the recent increased speed of computers and the need for high performance peripherals, the use of high speed serial data communications applications in integrated circuits built to physically interface to any given bus has increased correspondingly.
USB (Universal Serial Bus)
1
.
1
, has been the de facto external connectivity standard between computers and their peripherals in serial communications up to 12 Mbps (Million bits per second). As the need for faster communications and higher performance peripherals has grown, computer and peripheral manufacturers have responded with a new higher speed standard: USB
2
.
0
.
USB
2
.
0
increases the device data throughput up to 480 Mbps, 40 times faster than USB
1
.
1
devices while maintaining or improving on other USB
1
.
1
specifications such as the Microsoft Plug and Play feature, and numerous other technical specifications, some of which will be discussed in relation to the present invention. USB
2
.
0
even challenges FireWire (IEEE 1394) currently at 400 Mbps, as the serial interface of the future. Three speed modes are available under the new USB
2
.
0
standard: high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps).
Conventionally, an incoming serial data stream may be NRZI (Non-Return-to-Zero Inverted) encoded and bit stuffed. NRZI is a data transmission method in which the polarity of the bit is reversed whenever a 0 bit is encountered, and a static voltage level is transmitted whenever a 1 bit is encountered as illustrated in
FIG. 1
, and designated at reference numeral
110
. NRZI thus uses the presence or absence of a transition to signify a bit (indicating a logical 0 by inverting the state). Combined with bit-stuffing, where an extra 0 bit is inserted after every six consecutive 1 bits, this data encoding causes a guaranteed transition every 7 bit times when a data payload would be all 1 bits. Every transition gives the CDR circuit phase information that it uses to align it's recovered clock to the phase of the incoming data. The less time between transitions, the less phase error which is to be expected caused by frequency offset. Other techniques used are, for example,
8
b
-
10
b
coding similar to 1394 and Ethernet.
The structure of the data stream follows a specific communications protocol, which defines the rules for sending a block of data (each known as a Protocol Data Unit (PDU)) (e.g.,
150
of
FIG. 2
) from one node in a network to another node. The exchanged PDUs comprises three parts: a sync sequence
160
, a packet payload (also known as a Service Data Unit (SDU))
170
, and an End of Packet (EOP)
180
. The protocol does not define or constrain the data carried in the payload portion
170
of the data block. The protocol does, however, specify the format of the sync sequence.
Packet switching refers to protocols in which a longer message (the data) exceeding a network-defined maximum length is divided into short message packets before they are transmitted. Each packet, with an associated header with information for routing the packet from origination to destination, is then transmitted individually and can even follow different routes to its destination. Once all the packets forming a message arrive at the destination, they are recompiled into the original message. Most modern Wide Area Network (WAN) protocols, including the successful TCP/IP protocol, as well as X.25, and Frame Relay, are based on packet-switching technologies.
A fundamental difference between packet communication and conventional, continuous-type communication is that the data is formed into packets as described above. When there is no data to be sent, the bus is put into an ideal state that shows no change in voltage levels. Continuous-type protocols is would fill the idle time within a frame with well-known “idle” patterns which are used to occupy the link when there is no data to be communicated. A packet network equipment discards the “idle” patterns between packets and processes the entire packet as one piece of data. The equipment examines the packet header information (PCI) and then either removes the header (in an end system) or forwards the packet to another system. If the out-going link is not available, then the packet is placed in a queue until the link becomes free. A packet network is formed by links which connect packet network equipment.
In the packet switching used in USB
2
.
0
at 480 Mbps, one portion of the packet header
160
will contain at least 12 sync bits indicated by an alternating pattern, intended to allow the sending and receiving clocks time to synchronize. The packet payload
170
will contain up to 1024 bits, while the end-of-packet
180
contains 8 bits.
The incoming data stream is assumed to be sent with a clock of the same frequency as the local clock used in the receiving system, but shows all jitter components of an electrical transmission over a bandwidth limited media (e.g., data dependant cycle to cycle jitter).
A conventional linear clock and data recovery (CDR) circuit attempts to recover the original transmitting clock by utilizing a phase detector (PD) or alternatively a phase-frequency detector (PFD), and source a charge pump followed by a VCO of an analog PLL. The resulting change in phase and frequency is sourced back to the PD/PFD to be compared to the next data. These conventional linear techniques use an analog PLL, which need an undefined number of transitions, are dependant on the PLLs bandwidth, the data-rate to VCO frequency ratio and more. In addition, data derived by these conventional linear techniques cannot be guaranteed by the USB synch packet (typically N×10e3 needed vs 6 available in USB FS mode).
The capture range of a PLL is typically narrow, and usually requires the help of a frequency acquisition aid and special training sequences which have the disadvantage of limited availability.
Other conventional plesiochronous techniques to minimize the effect of metastable readings give unreliable phase information. To do so, most of these techniques try to average the results before selecting a new phase. This also requires a continuous bitstream that is not available in USB applications.
The analog types require many special analog components, including rectifier component(s), differentiator component(s), etc. These components are difficult to implement in ASIC devices, and when not carefully designed may not function properly under all conditions. The digital implementations have at most +/−50% usable frequency range, but are often narrower depending on the implementation and the statistics of the input data.
For a number of reasons such as bus turn around timing (the time measured at the USB host controller, from the sending of a request to the farthest bus subscriber, until receipt of an acknowledge package), a USB HUB is allowed to strip-off a defined number of sync bits during the HS repeater mode which results in a minimum sync pattern of 12 alternating bits at the receiver of a subscriber. Under FS conditions the sync field consists of 6 bits from the start. This is not enough sync bits for conventional CDR techniques.
Another prior art CDR methodology is illustrated in FIG.
3
and designated at reference numeral
200
. The CDR
200

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