Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1997-08-06
2000-02-15
Thai, Tuan V.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711205, 711207, G06F 1200
Patent
active
060264764
ABSTRACT:
A fast, fully associative translation lookaside buffer (TLB) with the ability to store and manage information pertaining to at least two different page sizes is disclosed. The TLB utilizes a tag array with tag lines and a data array with corresponding data lines. Within the tag array, each tag line incorporates a control cell which selectively enables or disables comparisons of tag bits to corresponding bits from an input address to the TLB. Within the data array, each data line incorporates control cells and multiplexing data cells to selectively determine whether bits in the physical address output of the TLB will be the derived from of the contents of the multiplexing data cells or bits from the input address. The use of control cells in the tag array and control cells and multiplexing data cells in the data array thereby provides for the ability to store and manage information pertaining to at least two different page sizes in a single TLB.
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Intel Corporation
Thai Tuan V.
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