Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-06-28
2001-06-19
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S189050, C365S210130, C365S230080, C365S203000
Reexamination Certificate
active
06249471
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to high-speed semiconductor memories. More particularly, and not by way of any limitation, the present invention is directed to compilable memory instances having a fast differential output circuit for rapidly transferring data from tri-statable sense amplifiers (“sense amps”) to selected outputs associated therewith.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that analog blocks, non-volatile memory, random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take hundreds of staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory is a key technology driver for SOC design. It is also well known that performance parameters such as access time, overall memory cycle time, et cetera, play a pivotal role in designing a memory circuit, whether provided in an embedded SOC application or as a stand-alone device. For high speed memories, accordingly, it is desirable that each of the following constituent components of the memory cycle time is minimized as much as possible: clock-to-wordline selection; cell-to-sense amp; and sense amp-to-output. Because the teachings of the present invention are particularly directed to reducing the time delay involved in the sense amp-to-output portion of the cycle time, a brief description of sense amp functionality with respect to RAMs (e.g., Static Random Access Memory or SRAM) is immediately set forth hereinbelow.
RAMs comprising a plurality of memory cells are typically configured as an array of rows and columns, with one or more I/Os (i.e., ×4, ×8, ×16, etc. configurations). Also, such memories may be provided in a multi-bank architecture for applications where high density, high speed and low power are required. Regardless of the architecture and type, each RAM cell is operable to store a single bit of information. Access to this information is facilitated by activating all memory cells in a given row and outputting the data onto bitlines associated with a selected column for providing the stored data value to the selected output. Once the data is disposed on the bitlines, voltage levels on the bitlines begin to separate to opposite power supply rails (e.g., V
DD
and ground), and a sense amp is utilized to latch the logic levels sensed on the bitlines after they are separated by a predetermined voltage difference, typically 10% or less of V
DD
. Furthermore, the sense amp is usually provided as a differential sense amp, with each of the memory cells providing both a data signal and a data-bar signal on the complementary bitlines (i.e., data lines) associated with each column. In operation, prior to activating the memory cells, the bitlines are precharged and equalized to a common value. Once a particular row and column are selected, the memory cell associated therewith is activated such that it pulls one of the data lines toward ground, with the other data line remaining at the precharged level, typically V
DD
. The sense amp coupled to the two complementary bitlines senses the difference between the two bitlines once it exceeds a predetermined value and the sensed difference is indicated to the sense amp as the differing logic states of “0” and “1”.
There are two common types of sense amps utilized for memory devices: one being a current mirror differential sense amp and the other being a clocked-latch type differential sense amp. It is well known that clocked-latch type sense amps are generally more advantageous than current mirror sense amps because they dissipate less power and work better at low voltages. Further, circuitry for implementing a clocked-latch type sense amp utilizes less area.
Even where the clocked-latch type sense amps are employed for memory devices, certain deficiencies and shortcomings exist with respect to the memory cycle time performance. First, usually several stages are required between the sense amp circuitry and corresponding output of the memory instance such that there is a significant delay in transferring the data latched in the sense amp to the output node. Such delay is not desirable in many high-speed applications.
Further, in multi-bank memory architectures prevalent in certain applications, signal paths between the sense amp circuitry and different corresponding outputs are not only variable but traverse longer distances as well. The sense amp-to-output performance in such applications using conventional solutions is also not satisfactory.
SUMMARY OF THE INVENTION
Accordingly, the present invention advantageously provides a full V
DD
signal swing differential output path circuit for rapidly transferring a latched data value on a pair of complementary “global” data nodes (referred to as Q
T
and Q
B
) to a single-ended output of a compilable memory instance during a memory access operation. In a presently preferred exemplary embodiment of the present invention, at least one tri-statable sense amplifier (sense amp) is disposed between the complementary global data nodes which operates to sense a small differential voltage between a pair of complementary bitlines (BIT and BITB) disposed in a bank of memory storage cells during an access operation associated therewith. A first output of the sense amp is coupled to one of the complementary global data nodes (Q
B
) and the complementary output of the sense amp is coupled to the other complementary global data node (Q
T
) to quickly drive either Q
T
or Q
B
from V
DD
to ground as soon as the bitline polarity is sensed by the sense amp. The output structure then quickly takes the full differential value between Q
T
and Q
B
and drives the single-ended output of the memory instance rapidly to either V
DD
or ground. A pair of precharge pull up devices are provided for precharging the complementary global data nodes Q
T
and Q
B
to a predetermined voltage, e.g., V
DD
. The precharge pull up devices preferably comprise P-channel MOS (PMOS) devices and are actuatable by an active low precharge signal. A CMOS pass gate actuatable by an output enable signal is disposed on the Q
B
data path, wherein the pass gate operates to drive an output pull up device coupled to the output of the memory instance. A NOR gate is coupled to the Q
T
data path and an inverted signal derived from the output enable signal, wherein the NOR gate operates to drive a output pull down device coupled to
Fears Terrell W.
Smith ,Danamraj & Youst, P.C.
Virage Logic Corp.
LandOfFree
Fast full signal differential output path circuit for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fast full signal differential output path circuit for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast full signal differential output path circuit for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2446696