Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Patent
1998-07-17
2000-10-03
Pan, Daniel H.
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
710 64, 370422, 370382, 714 21, 714 10, G06F 1120, G06F 1340
Patent
active
061286877
ABSTRACT:
Logic circuitry (70, 80, 90) for performing fault detection in a microprocessor (5) is disclosed. The fault detection logic circuitry (70, 80, 90) may be implemented into a scheduler (50) in a floating-point unit (31). Mask register (M) bit positions (M.sub.0 through M.sub.7) store state information relative to registers (52) or other resources in the microprocessor (5) that is to be interrogated upon scheduling of an instruction. The instruction includes an encoded address communicated on register address lines (SA) that is received by the fault detection logic circuitry (70, 80, 90). Pass gates (72) are controlled by the encoded address on the register address lines (SA) to generate a fault indicator (FLT). Partitioning of the decoding of the encoded address may be utilized for optimization of the fault detection operation.
REFERENCES:
patent: 5058104 (1991-10-01), Yonehara et al.
patent: 5168499 (1992-12-01), Peterson et al.
Bui Duc Q.
Dao Tuan Q.
Donaldson Richard L.
Laws Gerald E.
Marshall, Jr. Robert D.
Pan Daniel H.
Texas Instrumenets Incorporated
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