Fast exception processing

Details Fast exception processing Fast exception processing

1999-05-04

2003-09-23

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S140000, C712S244000

Reexamination Certificate

active

06625693

ABSTRACT:

FIELD
This invention relates generally to exception processing, and more particularly to fast exception processing in the context of pipelined processors.
BACKGROUND
The speeds at which processors perform are increasing due to constantly increasing computing needs. There are a number of ways to increase the speed of the processor, such as decreasing cycle time and reducing the average number of cycles required to execute many instructions collectively.
A well known way of increasing performance in processors and microcontrollers is to overlap the steps of different instructions using a technique called pipelining. To pipeline instructions, the various steps of instruction execution are performed by independent units called pipeline stages. As the number of stages is increased, while keeping the work done by any given instruction constant, the processor is said to be more heavily pipelined. Each instruction progresses from stage to stage, ideally with another instruction progressing in lock step only one stage behind. Thus, there can be as many instructions in execution, as there are pipeline stages. Each stage of execution is designed to perform its work within the processor's basic machine cycle. Thus, although each instruction requires as many cycles to perform as there are pipeline stages, a pipelined processors throughput is one instruction per cycle. In this manner, pipelining reduces the average number of cycles required to execute many instructions collectively, though it does not reduce the total amount of time required to execute any single instruction, by permitting the processor to handle more than one instruction at a time. Thus, pipelining is an architectural technique for improving performance over what can be achieved via processor circuit design improvements alone.
When a processor is executing, exceptions may occur. An exception is a special condition or event that unpredictably changes the normal flow of control in a program. The software that handles an exception is typically called an exception handler or handler. Generally, exceptions are either fatal or non fatal. A fatal exception is an exception which results in abrupt termination of execution. A non fatal exception does not result in abrupt termination of execution.
When a non-fatal exception occurs, typically the operating system (OS) must be called and the pipeline is flushed. This causes a severe degradation of performance depending on the type of application the processor is engaged in. If the non-fatal exception is occurring frequently, severe degradation of performance occurs.
One solution has been to hardwire exception processing. This can result in the instruction pointer not changing and as a result no flushing of the pipeline occurs. An example of this solution is Intel Corporation's 32-bit form iA32 of the industry standard architecture (ISA). When a translation look aside buffer (TLB) miss occurs, the ISA actually handles the translation cache miss in hardware, by performing “page table walk” in microcode, as it attempts to find the missing translation. A TLB is a table used in a virtual memory system, which lists the physical address page number associated with each virtual address page number. A TLB is used in conjunction with a cache whose tags are based on virtual addresses. The virtual address is presented simultaneously to the TLB and to the cache so that cache access and virtual to physical address translation can proceed in parallel (the translation is done “on the side”). If the requested address is not cached then the physical address is used to locate the data in main memory. The alternative would be to place the translation table between the cache and main memory so that it will only be activated once there was a cache miss. Since the code to handle the TLB miss event is “hardwired”, no instruction fetch is needed to retrieve the instructions needed for the handler. As a result, no pipeline flush is needed since there is no change in the instruction pointer as a result of the TLB miss event. This approach eliminates the performance degradation caused by the pipeline being flushed. This works but has some drawbacks. One drawback to hardwired control is that only a limited number of exceptions may be hardwired. This approach is not entirely satisfactory because processors generally do not perform the same function all the time. For example, having the TLB miss hardwired does not benefit some applications such as one where only numerical calculations are involved. Another drawback to hardwired control is that hardwired control is fixed and therefore inflexible.
Other architectures such as the reduced instruction computing (RISC) architectures call the operating system more often in the event of an exception. This allows software to determine how to handle the exception but at the cost of performance. The present invention handles exceptions in a faster and more flexible manner.


REFERENCES:
patent: 5305455 (1994-04-01), Anschuetz et al.
patent: 5634108 (1997-05-01), Freeman
patent: 5909574 (1999-06-01), Meyer
patent: 5966529 (1999-10-01), Sollars
patent: 6003129 (1999-12-01), Song et al.
patent: 6012125 (2000-01-01), Tran
patent: 6038645 (2000-03-01), Nanda et al.
patent: 6141740 (2000-10-01), Mahalingaiah et al.
patent: 6157988 (2000-12-01), Dowling
patent: 6170051 (2001-01-01), Dowling
patent: 6295580 (2001-09-01), Sturges et al.

Affiliated with

Also associated with

Rating

Fast exception processing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fast exception processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast exception processing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3020459