Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-08-24
2002-04-23
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290, C365S218000
Reexamination Certificate
active
06377488
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of electronic data storage devices. More particularly, the present invention relates to non-volatile semiconductor memory devices and reducing the time required to erase data in non-volatile semiconductor memory devices.
2. Description of the Related Art
Many electronic devices, such as computers, personal digital assistants, cellular telephones, digital cameras and similar systems and devices include processors and memory. The memory is used to store computer programs to be executed by the device and/or data operated on by the processors to achieve the functionality of the device. Many devices and systems require that this information be retained in permanent storage
on-volatile medium so that the data and computer programs is not lost when power is removed.
Conventional semiconductor memory devices store information in locations termed memory cells. Internally, data is organized in an array of sectors, each comprising a plurality of memory cells. Conventional semiconductor memory devices allow only a single bit of data to be written or erased at a given time. The typical memory cell comprises an access transistor and a storage element such as a capacitor. The data is represented in binary notation with a “1” or a “0”, depending on the charge stored at the location. Such devices, however, require constant ambient power in order to retain the charge. Therefore, the data stored in such memory devices are susceptible to power loss.
Semiconductor memory devices that do not require ambient power to retain the data stored therein have been developed. These devices have been termed “non-volatile” semiconductor memory devices. In common designs for non-volatile semiconductor memory devices, data is erased in units of memory called sectors. and cannot be erased at the byte level. Each sector is partitioned into segments termed a page. Data is accessed for reading and programming by page, while the entire sector is accessed for erasing.
One-type of non-volatile memory device that can be used is termed Erasable Programmable Read Only Memory (“EPROM”). While conventional EPROM's provide reliable non-volatile storage, they may not be able to be reprogrammed in the field in a practical matter. For example, EPROM's typically require exposure to Ultraviolet light to erase. This often requires that the device be removed from its host to be erased. In many applications, removing the memory is not practical to reprogram. One type of EPROM is the Electrically Erasable Programmable Read Only Memory (EEPROM). An EEPROM is similar to an EPROM, but can be electrically reprogrammed with voltage pulses and without special hardware. An EEPROM has the disadvantages of being expensive and having a relatively limited life span, according to the number of erased and write operations.
Flash memory (or Flash RAM) is another form of non-volatile memory devices. Flash memory devices use a memory cell transistor with a floating gate structure. The typical memory cell in a flash memory device comprises an access transistor and a storage element, such as a floating gate. Data in the flash memory device are programmed or erased by accumulation or depletion of charge, respectively, on a thin insulating film between a substrate and a floating gate. Programming of the memory cells occurs by applying a sufficient voltage difference to the transistors to cause excess electrons to accumulate on the floating gate. The accumulation of the additional electrons on the floating gate raises the charge on the gate and the transistor's threshold voltage. The transistor's threshold voltage is raised sufficiently above that of the applied voltage during read cycles so that the transistor does not turn on during the read cycles. Therefore, a programmed memory cell will not carry current, representing the logical value “0.” The erasure of a sector of data is caused by a process in which a voltage difference is applied to the transistor in each memory cell of the sector to cause the excess electrons on the floating gate in each transistor to evacuate the film. Thereby the transistor's threshold voltage is lowered below that of the voltage potential applied to the transistor to read data. In the erased state, current will flow through the transistor. When the read voltage potential is applied, the current will flow through the transistor of the memory cell, representing a logical value “1” stored in the memory cell.
Prior flash memory devices could be erased only by erasing the entire memory array. Selective erasure was not possible. To somewhat alleviate this problem, data stored in flash memory devices are organized into sectors where each sector contains a portion of the total bytes of data storage available. This arrangement allows the option of erasure of the memory device sector-by-sector. While typical flash memory devices are still incapable of byte by byte erasure, data may be programmed in the flash memory byte by byte. It will be appreciated that the granularity by which a flash memory device can be programmed or erased may vary and that granularities down to the bit level programming/erasure are contemplated.
In order to erase a flash memory, typically a complex process must be followed. At the present time, when multiple memory sectors need to be erased, they are erased in series. Each memory sector that needs to be erased is singly and sequentially until each memory sector so identified has been erased. For each sector an erasure cycle and a verify cycle is performed. During the erasure cycle, an erase voltage potential is applied to each memory cell in the selected memory sector to be erased. During the verify cycle, it is determined whether each memory cell in the selected sector is erased. When it is determined that the selected memory is not erased according to the verify cycle, the erase cycle on the selected memory sector is repeated. The erase and verify cycles are repeated until it is determined that each memory cell in the selected memory sector is erased according to the verify cycle. When it is determined that each memory cell in the selected memory sector is erased, one of the remaining plurality of memory sectors is selected and the erase and verify cycles performed on that memory sector. The erase and verify cycles are sequentially repeated on each of the memory sectors until each of the memory sectors is erased.
Because the erasure rate varies from sector to sector, the time necessary to erase each sector will also vary. Therefore, the erase cycle extends for a sufficient time to erase the memory cells in the memory sector and the verify cycle determines whether the erase was sufficient to erase all memory cells in the memory sector.
The erasure cycle of a sector of memory cells is comparatively slower than the verify cycles. During the erasure cycle, the voltage potential must be applied for sufficient time to allow the evacuation of electrons on the floating gate. For each memory sector, each erasure cycle will last approximately on the order of seconds, while each verify cycle lasts approximately on the order of milliseconds. Thus, the erasure is several thousands times longer than the verify cycle. Too frequent applications of the erasure voltage potential or application of the erasure voltage for extended periods of time may result in damage to the transistor.
Accordingly, there is a need in the art for a circuit and method that reduces the erase time of a semiconductor memory.
BRIEF SUMMARY OF THE INVENTION
By way of example only, a memory device comprises a plurality of memory sectors, each having a plurality of the memory cells that store data, and an erase-verify circuit, which erases memory sectors in parallel, by simultaneously erasing a plurality of memory sectors. The erase-verify circuit simultaneously erases a plurality memory sectors, and verifies that the memory cells in a selected memory sector of the plurality of memory sectors is erased. When it determin
Kim Yong
Nguyen Kendra
Advanced Micro Devices , Inc.
Dinh Son T.
LandOfFree
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