Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-25
2011-01-25
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C326S031000, C326S041000, C326S101000
Reexamination Certificate
active
07877719
ABSTRACT:
Integrated circuit apparatus and methods are described for inserting multi-Vddbuffers within an interconnection tree during routing toward minimization of power under a delay constraint. Insertion of level converters is not necessary within the routing trees of the interconnect tree despite the insertion of the multi-Vddbuffers. Techniques are described for controlling the dramatic complexity increment due to simultaneous delay and power consideration and increased buffer choices. Overhead reduction techniques are taught including: sampling based techniques, prediction based pruning techniques (PSP) and (PMP), and escape grid reduction, each of which are directed to multi-Vddbuffer insertion. The resultant integrated circuits are routed with substantial power reductions over conventional routing.
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Kik Phallaka
O'Banion John P.
The Regents of the University of California
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