Fast dual-rail dynamic logic style

Details Fast dual-rail dynamic logic style Fast dual-rail dynamic logic style

2005-01-04

2005-01-04

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C326S093000

Reexamination Certificate

active

06838910

ABSTRACT:
A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

REFERENCES:
patent: 5384493 (1995-01-01), Furuki
patent: 5455528 (1995-10-01), Partovi et al.
patent: 5777491 (1998-07-01), Hwang et al.
patent: 5917355 (1999-06-01), Klass
patent: 6028454 (2000-02-01), Elmasry et al.
patent: 6046606 (2000-04-01), Chu et al.
patent: 6236240 (2001-05-01), Hill
patent: 6331791 (2001-12-01), Huang
patent: 6573755 (2003-06-01), Fletcher et al.

Affiliated with

Also associated with

Rating

Fast dual-rail dynamic logic style does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fast dual-rail dynamic logic style, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast dual-rail dynamic logic style will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3429319