Fast domain switch and error recovery in a secure CPU architectu

Details Fast domain switch and error recovery in a secure CPU architectu Fast domain switch and error recovery in a secure CPU architectu

1997-12-19

2000-01-11

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

G06F 1100

Patent

active

060147571

ABSTRACT:
In order to gather, store temporarily and efficiently deliver safestore information in a CPU having data manipulation circuitry including a register bank, first and second serially oriented safestore buffers are employed. At suitable times during the processing of information, a copy of the instantaneous contents of the register bank is transferred into the first safestore buffer. After a brief delay, a copy of the first safestore buffer is transferred into the second safestore buffer. If a call for a domain change (which might include a process change or a fault) is sensed, a safestore frame is sent to cache, and the first safestore buffer is loaded from he second safestore buffer rather than from the register bank. Later, during a climb operation, if a restart of the interrupted process is undertaken and the restoration of the register bank is directed to be taken from the first safestore buffer, this source, rather than the safestore frame stored in cache, is employed to obtain a corresponding increase in the rate of restart. In one embodiment, the transfer of information between the register bank and the safestore buffers is carried out on a bit-by-bit basis to achieve additional flexibility of operation and also to conserve integrated circuit space.

REFERENCES:
patent: 4530052 (1985-07-01), King et al.
patent: 4823256 (1989-04-01), Bishop et al.
patent: 4914576 (1990-04-01), Zelley et al.
patent: 5553232 (1996-09-01), Wilhite et al.
patent: 5905857 (1999-05-01), Buzby et al.

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