Fast digital sample resolution circuit

Details Fast digital sample resolution circuit Fast digital sample resolution circuit

1982-12-13

1984-09-25

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307475, 307528, 307577, 307583, H03K 3353, H03K 526, H03K 1716, H03K 19096

Patent

active

044737602

ABSTRACT:
A fast digital sample resolution circuit comprising a dynamic ratioless inverter coupled to a static ratioed inverter, with positive capacitive feedback. A transistor node is precharged to one logic level. Any positive transition of an input signal causes the precharged node to begin discharging, thereby causing a capacitive feedback signal to rapidly reinforce the input signal. The resolution circuit minimizes the probability that its output is an ambiguous logic signal.

REFERENCES:
patent: 3761739 (1973-09-01), East et al.
patent: 3935474 (1976-01-01), Komarek
patent: 3935475 (1976-01-01), Margolies
patent: 3947697 (1976-03-01), Archer et al.
patent: 3953744 (1976-04-01), Kawagoe
patent: 4011465 (1977-03-01), Alvarez, Jr.
patent: 4317053 (1982-02-01), Shaw et al.
patent: 4380083 (1983-04-01), Andersson et al.

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