1995-06-21
1997-01-07
Gordon, Paul P.
Excavating
371 402, 371 511, G11C 2900
Patent
active
055924999
ABSTRACT:
A semiconductor memory device includes a memory cell array for storing information and parity bits, a register circuit for temporarily holding the information and parity bits in respective bit register circuits, and an XOR circuit for detecting an error of logical values of the information and parity bits in accordance with a predetermined verifying matrix. The XOR circuit includes a plurality of XORs each having an input line pair for receiving information in a first direction, an input line pair for receiving information in a second direction perpendicular to the first direction, and an output line pair outputting XOR logical values in the second direction.
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Gordon Paul P.
Oakes Brian C.
OKI Electric Industry Co., Ltd.
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