Electrical computers and digital data processing systems: input/ – Intrasystem connection – System configuring
Reexamination Certificate
2001-07-27
2004-06-01
Perveen, Rehana (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
System configuring
C710S305000, C710S107000, C710S061000, C713S503000, C711S167000
Reexamination Certificate
active
06745271
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data transfer system which has multiple memory modules and a controller for controlling data read and write operations of the memory modules and provides synchronous data transfer between each memory module and the controller. Further, the present invention specifically relates to a technique of improving significantly efficiency in data transfers by transferring both read data and write data over the same bus.
As the performance of microprocessor units (MPUs) used in control systems has improved, the capacity of IC memories used has increased to 256 megabits, 1 gigabits. Under such a circumstance, how to transfer large amounts of data efficiently has become increasingly important.
In U.S. Pat. No. 5,432,823, there is disclosed a data transfer system which realizes fast data transfer.
FIG. 1
is a schematic representation of the data transfer system disclosed in that U.S. patent. This system is provided with a clock generator (CG)
301
, a plurality of memory modules
302
, and a controller
303
. The memory modules
302
and the controller
303
are arranged in parallel. A clock interconnect line
304
is provided to go and return along the arrangement of the memory modules and the controller. Further, a data bus
305
is provided along the arrangement of the memory modules and the controller.
Clock pulses, generated by the clock generator
301
, are transferred as clock TCLK to the memory modules
302
and the controller
303
in sequence over the go portion of the clock line
304
. After passing through the turnaround point from the go portion to the return portion, the clock pulses are transferred as clock RCLK in the direction opposite to the direction in which they are transferred over the go portion to the controller
303
and the memory modules
302
in sequence. Eventually, the clock pulses are transferred to a location near the clock generator
301
. In this case, the controller
303
is located near the turnaround point of the clock line
304
.
Data transfer between each of the memory modules
302
and the controller
303
is made via the data bus
305
.
In general, in data transfer between each of the memory modules at different locations and the controller under clock-synchronized control, data collisions will occur on the data bus unless propagation delays of clock pulses are taken into consideration in advance.
The conventional system of
FIG. 1
monitors the clock TCLK and the clock RCLK in the controller
303
and each of the memory modules
302
to take the following measures for avoidance of data collisions on the data bus.
That is, as shown in a timing chart of
FIG. 2
, in the neighborhood of the turnaround point of the clock line
304
, the clock TCLK and the clock RCLK are in phase with each other, whereas, in the neighborhood of the clock generator
301
, they are out of phase with each other, i.e., the clock RCLK is delayed with respect to the clock TCLK. The timing A in the middle between the clock TCLK and the clock RCLK does not depend on the location on the clock line
304
and, at any location, is midway between the clocks. If, therefore, each memory module and the controller make data transfers taking into consideration the intermediate timing A and the phase difference between the clocks TCLK and RCLK, then data collisions on the data bus
305
can be avoided.
However, when clock pulses of shorter periods (higher frequencies) are used to increase further efficiency in data transfers or the data bus is made longer as a result of connecting more memory modules so as to increase the system memory capacity, the clock propagation delay may exceed one cycle period of clock pulses.
In this case, as shown in a timing chart of
FIG. 3
, the erroneous timing A is obtained instead of the timing B which is originally required and corresponds to the middle of the time interval between the clocks TCLK and RCLK. For example, assume that, when the controller
303
is located in the neighborhood of the clock generator
301
, the clock TCLK is transferred over the clock line
304
and delayed by more than one clock cycle period, and a positive-going edge of the return clock RCLK corresponding to a positive-going edge of the go clock TCLK at time t
1
occurs at time t
3
. Then, when the intermediate timing is simply taken between positive-going edges of the clocks TCLK and RCLK, the intermediate timing A will be erroneously taken between the time t
1
and the time that the clock RCLK rises immediately after t
1
. The correct intermediate timing B in this case is the time t
2
between t
1
and t
3
.
Thus, the relationship between the clocks TCLK and RCLK alone cannot decide whether or not a phase displacement of more than one clock cycle period has occurred between the clocks TCLK and RCLK, so that erroneous intermediate timing results.
The data bus is employed for transfer of both read data and write data from and to the memory modules. However, since data items “1” and “0” in data are generally represented by voltage levels, it is required to divide definitely the read data transfer timing and the write data transfer timing. For this reason, in order to make read data and write data transfers concurrently and sharply increase the data transfer efficiency approximately twofold, it is required to divide the data bus into a read data bus
306
and a write data bus
307
as shown in FIG.
4
.
However, this approach doubles the number of data bus wirings, resulting in a twofold increase in the number of pins of each of the memory modules and the controller and hence increases in area and cost.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a fast data transfer system which permits data transfers to be made at high speed without increasing the number of data buses.
According to the present invention there is provided a fast data transfer system comprising: a plurality of memory modules; a controller located adjacent to the memory modules in a direction where the memory modules are arranged and communicating data with each of the memory modules; a clock generator for generating a first basic clock and a second basic clock having a cycle period n (n is either 2 or 4) times longer than a cycle period of the first basic clock; two clock lines each having a go line portion and a return line portion, which extend in opposite directions along the arrangement of the memory modules and the controller, the first and second basic clocks generated by the clock generator being respectively inputted to the two clock lines at ends of their respective go line portions and transferred over the two clock lines, and the first and second basic clocks transferred over the go and return line portions of the respective first and second clock lines being inputted to each of the memory modules and the controller, data input/output operations of each of the memory modules and the controller being performed in synchronism with the first and second basic clocks; and control circuits provided in each of the memory modules and the controller and including a timing signal generating circuit responsive to first and second basic go clocks transferred over the go line portions of the clock lines and first and second basic return clocks transferred over the return line portions of the clock lines for generating a intermediate timing signal having a timing which positioned in the middle of a phase displacement that occurs between the first basic go clock and the first basic return clock within a period n (n is either 2 or 4) times the cycle period of the first basic clock.
In addition, according to the present invention there is provided a fast data transfer system comprising: a plurality of memory modules; a controller for communicating data with each of the memory modules; and a data bus connecting the memory modules and the controller, wherein each of the memory modules and the controller having a data input/output circuit for allowing the value of and the direction of a current that flows thr
Kabushiki Kaisha Toshiba
Kim Harold
LandOfFree
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