Fast clock acquisition enable method using phase stir...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S316000, C375S215000, C370S503000, C327S331000, C327S147000, C327S156000, C329S325000, C342S103000, C455S165100, C455S260000

Reexamination Certificate

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07421053

ABSTRACT:
Systems and methods for aligning the phase of a PLL with an incoming data signal. In one embodiment, when a data signal is received in a PLL, a phase perturbation signal is generated and injected into the PLL. The PLL then performs a phase alignment procedure to lock on to the received data signal. The phase perturbation signal is a damped sinusoidal oscillation that is injected into the PLL when each of a plurality of data packets is received. The perturbation signal has an amplitude sufficient to bump the PLL out of a quasi-stable state around 180 degrees out of phase with the incoming data signal, but is damped to less than a degree of phase shift within 30 ns of being injected.

REFERENCES:
patent: 3649123 (1972-03-01), Ulicki
patent: 4359692 (1982-11-01), Ryan
patent: 4873457 (1989-10-01), Sanielevici
patent: 4878474 (1989-11-01), Hack, Jr.
patent: 5040242 (1991-08-01), Tsuchiya et al.
patent: 5430766 (1995-07-01), Ota et al.
patent: 5570052 (1996-10-01), Fonderie et al.
patent: 5764598 (1998-06-01), Okayasu
patent: 6069499 (2000-05-01), Cho et al.
patent: 6178213 (2001-01-01), McCormack et al.
patent: 6256557 (2001-07-01), Avila et al.
patent: 6509990 (2003-01-01), Roberts
patent: 6735162 (2004-05-01), Armitage et al.
patent: 6735260 (2004-05-01), Eliezer et al.
patent: 6771719 (2004-08-01), Koyama et al.
patent: 7058150 (2006-06-01), Buchwald et al.
patent: 2001/0021051 (2001-09-01), Kim
patent: 2002/0027692 (2002-03-01), Uchiyama et al.
patent: 2002/0057479 (2002-05-01), Takeshita et al.
patent: 38 31 296 (1989-04-01), None
patent: 09246973 (1997-09-01), None

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