Fast charging MOS capacitor structure for high magnitude voltage

Details Fast charging MOS capacitor structure for high magnitude voltage Fast charging MOS capacitor structure for high magnitude voltage

1993-07-09

1994-08-23

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257313, 257532, 257535, 361303, H01L 2702, H01G 1005

Patent

active

053410092

ABSTRACT:
Depletion layer depth and semiconductor real estate occupation area shortcomings of conventional MOS capacitor architectures that are formed on lightly doped semiconductor material are obviated by augmenting the MOS capacitor structure with a pair of opposite conductivity type, high impurity concentration regions, both of which are directly contiguous with the lightly doped lower plate layer that underlies the capacitor's dielectric layer, and connecting both of these auxiliary heavily doped regions to a common capacitor electrode terminal for the lower plate of the capacitor. If a high negative charge is applied to the upper plate overlying the thin dielectric layer, holes are readily supplied by the auxiliary P+ region. Conversely, if a high positive charge be applied to the upper plate, electrons are readily supplied by the auxiliary N+ region. By connecting both the auxiliary N+ and P+ regions together, a deep depletion condition is prevented for either polarity of the applied voltage. An application of the MOS capacitor structure is its use in a single event upset immune memory cell formed on an insulating substrate. A pair of MOS capacitors having a structural configuration in accordance with the present invention are coupled between input and output nodes of a pair of cross-coupled MOSFET inverters that form the memory cell.

REFERENCES:
patent: 5083184 (1992-01-01), Eguchi

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