Fast carry-out scheme in a field programmable gate array

Details Fast carry-out scheme in a field programmable gate array Fast carry-out scheme in a field programmable gate array

1995-10-26

1997-10-07

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 40, H03K 19177

Patent

active

056752628

ABSTRACT:
A fast carry-out scheme in a field programmable logic array. The configurable logic blocks (CLBs) are arranged in columns. The carry-out signals are routed from the bottom CLB of a column to the top CLB of that column. The carry-out from the top-most CLB is then multiplexed onto a clock line that is normally used to conduct clocking signals to the CLBs. Instead of conducting clocking signals, the existing clock line is now used to route the carry-out signal onto a vertical longline spanning the entire height of the column. Eventually, the carry-out signal is routed from the longline to its destination CLB of the adjacent column via local interconnect resources.

REFERENCES:
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5267187 (1993-11-01), Hsieh et al.
patent: 5359242 (1994-10-01), Veenstra
patent: 5450021 (1995-09-01), Chiang
patent: 5481206 (1996-01-01), New et al.

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