Fast buffer pointer across clock domains

Details Fast buffer pointer across clock domains Fast buffer pointer across clock domains

2006-10-06

2009-06-30

Rinehart, Mark (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C713S400000, C713S401000, C375S354000

Reexamination Certificate

active

07555590

ABSTRACT:
Retiming circuitry for retiming a data signal transmitted from a first environment under control of a first clock signal to a second environment under control of a second clock signal, said first and second clock signals having a known repeat relationship, the retiming circuitry comprising a plurality of delay elements for delaying said data signal; a plurality of inputs connected to said delay elements for receiving said data signal at respectfully different delays; selection means for selecting the data signal at one of said inputs based on said known repeat relationship; and an output for outputting said selected data signal.

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