Fast bit-parallel Viterbi decoder add-compare-select circuit

Details Fast bit-parallel Viterbi decoder add-compare-select circuit Fast bit-parallel Viterbi decoder add-compare-select circuit

2006-10-31

2006-10-31

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C375S262000, C375S341000

Reexamination Certificate

active

07131055

ABSTRACT:
A Viterbi decoder includes an ACS unit that performs state metric updates for every symbol cycle. State metric updates involve adding the state metrics corresponding to a likely input symbol to the respective branch matrix, comparing the results of the additions to determine which is smaller, and selecting the smaller result for the next state metric. The ACS unit includes two parallel adders followed by a parallel comparator that generates a multiplexer-select signal. The outputs of the parallel adders are input into a multiplexer and the multiplexer-select signal is input into the multiplexer for a decision.

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