Fast and compact address bit routing scheme that supports variou

Details Fast and compact address bit routing scheme that supports variou Fast and compact address bit routing scheme that supports variou

1997-10-31

2000-08-22

Cabeca, John W.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

711 5, 711217, 711157, 711127, 711128, G06F 1208

Patent

active

061087459

ABSTRACT:
An address routing scheme supports a variety of memory sizes and interleaving schemes. In one embodiment, any address bit provided by the processor can be routed to any bank, row, or column bit, and can be used to generate any rank bit. This embodiment supports any type of interleaving scheme and memory modules constructed from a wide variety of DRAM chips. In another embodiment, a reduced routing function is used to generate rank bits and route address bits to subsets of bank, row, or column bits such that no route function encoding requires more than 3 bits. The second embodiment supports multi-cache line interleaving, cache effect interleaving, and DRAM page interleaving. Multi-cache line causes cache lines contained in small contiguous blocks to be contained in one DRAM page, while contiguous small contiguous blocks are stored on separate DRAM pages. Cache-effect interleaving greatly increases the probability that cache lines having the same index, but different tags, will be stored in different banks by routing one or more of the address bits corresponding with the bits immediately above the cache memory index field to either bank or rank bits. Finally, DRAM page interleaving causes contiguous (or proximate) DRAM pages to be stored in separate banks by routing one or more of the address bits corresponding with the bits immediately above the column boundary to either bank or rank bits.

REFERENCES:
patent: 5390308 (1995-02-01), Ware et al.
patent: 5696917 (1997-12-01), Mills et al.
patent: 5745913 (1998-04-01), Pattin et al.
patent: 5761695 (1998-06-01), Maeda et al.
patent: 5890221 (1999-03-01), Liu et al.

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