Fast accessible non-volatile semiconductor memory device

Details Fast accessible non-volatile semiconductor memory device Fast accessible non-volatile semiconductor memory device

1995-02-27

1997-07-08

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular connection

365154, 365156, 36518507, 36518528, 36518529, G11C 1124

Patent

active

056468857

ABSTRACT:
A non-volatile SRAM cell (MC) includes floating gate type transistors (1a, 1b) arranged between power supply nodes (4a, 4b) and storage nodes (A, B), and flip-flops (2a, 2b) holding signal potentials of the storage nodes. The floating gate type transistor has a drain connected to the power supply node, and a control gate connected to a control electrode node (5). Voltages are applied independently to the drains and the control gate of the floating gate type transistor, whereby a large amount of hot electrons are efficiently generated by avalanche breakdown and are accelerated to be injected into the floating gate. Removal of electrons is achieved by the voltages applied to the control gate and the drain. In the non-volatile SRAM cell utilizing the floating gate type transistor, injection and removal of electrons with respect to the floating gate are efficiently performed to change a threshold voltage for reliably storing information in a non-volatile manner.

REFERENCES:
patent: 4435786 (1984-03-01), Tickle
patent: 5051948 (1991-09-01), Watabe et al.
patent: 5051951 (1991-09-01), Maly et al.
patent: 5319593 (1994-06-01), Wolstenholme
patent: 5463586 (1995-10-01), Chao et al.
"A 14-NS 1-MBIT CMOS SRAM with Variable Bit Organization", Kohno et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1060-1066.

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